JAJSDJ5 July   2017 OPA196 , OPA2196 , OPA4196

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA196
    5. 6.5 Thermal Information: OPA2196
    6. 6.6 Thermal Information: OPA4196
    7. 6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
    8. 6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Protection Circuitry
      2. 7.3.2 EMI Rejection
      3. 7.3.3 Phase Reversal Protection
      4. 7.3.4 Thermal Protection
      5. 7.3.5 Capacitive Load and Stability
      6. 7.3.6 Common-Mode Voltage Range
      7. 7.3.7 Electrical Overstress
      8. 7.3.8 Overload Recovery
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Low-side Current Measurement
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 16-Bit Precision Multiplexed Data-Acquisition System
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Slew Rate Limit for Input Protection
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 TINA-TI(無料のダウンロード・ソフトウェア)
        2. 11.1.1.2 TI Precision Designs
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VS = (V+) – (V–) ±20
(+40, single supply)		 V
Signal input pins Voltage Common-mode (V–) – 0.5 (V+) + 0.5 V
Differential (V+) – (V–) + 0.2
Current ±10 mA
Output short circuit(2) Continuous Continuous Continuous
Temperature Operating –40 150 °C
Junction 150
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge OPAx196 Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V
V(ESD) Electrostatic discharge OPA196 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V
OPA2196 ±500 V
OPA4196 ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage, VS = (V+) – (V–) 4.5 (±2.25) 36 (±18) V
Specified temperature –40 125 °C

6.4 Thermal Information: OPA196

THERMAL METRIC(1) OPA196 UNIT
8 PINS 5 PINS
D (SOIC) DGK (VSSOP) DBV (SOT)
RθJA Junction-to-ambient thermal resistance 115.8 180.4 158.8 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 60.1 67.9 60.7 °C/W
RθJB Junction-to-board thermal resistance 56.4 102.1 44.8 °C/W
ψJT Junction-to-top characterization parameter 12.8 10.4 1.6 °C/W
ψJB Junction-to-board characterization parameter 55.9 100.3 4.2 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Thermal Information: OPA2196

THERMAL METRIC(1) OPA2196 UNIT
8 PINS
D (SOIC) DGK (VSSOP)
RθJA Junction-to-ambient thermal resistance 107.9 158 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 53.9 48.6 °C/W
RθJB Junction-to-board thermal resistance 48.9 78.7 °C/W
ψJT Junction-to-top characterization parameter 6.6 3.9 °C/W
ψJB Junction-to-board characterization parameter 48.3 77.3 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Thermal Information: OPA4196

THERMAL METRIC(1) OPA4196 UNIT
14 PINS
D (SOIC) PW (TSSOP)
RθJA Junction-to-ambient thermal resistance 86.4 92.6 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 46.3 27.5 °C/W
RθJB Junction-to-board thermal resistance 41.0 33.6 °C/W
ψJT Junction-to-top characterization parameter 11.3 1.9 °C/W
ψJB Junction-to-board characterization parameter 40.7 33.1 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)

at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = ±18 V ±25 ±100 µV
(V+) – 3.0 V < VCM < (V+) – 1.5 V See Common-Mode Voltage Range
VS = ±18 V,
VCM = (V+) – 1.5 V		 ±25 ±100
dVOS/dT Input offset voltage drift VS = ±18 V, VCM = (V+) – 3 V TA = –40°C to +125°C ±0.5 µV/°C
VS = ±18 V, VCM = (V+) – 1.5 V ±0.8
PSRR Power-supply rejection ratio TA = –40°C to +125°C ±0.3 ±1 µV/V
INPUT BIAS CURRENT
IB Input bias current ±5 ±20 pA
IOS Input offset current ±2 ±20 pA
NOISE
En Input voltage noise (V–) – 0.1 V < VCM < (V+) – 3 V f = 0.1 Hz to 10 Hz 1.4 µVPP
(V+) – 1.5 V < VCM < (V+) + 0.1 V f = 0.1 Hz to 10 Hz 7
en Input voltage noise density (V–) – 0.1 V < VCM < (V+) – 3 V f = 100 Hz 18 nV/√Hz
f = 1 kHz 15
(V+) – 1.5 V < VCM < (V+) + 0.1 V f = 100 Hz 53
f = 1 kHz 24
in Input current noise density f = 1 kHz 1.5 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage range (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio VS = ±18 V,
(V–) – 0.1 V < VCM < (V+) – 3 V		 120 140 dB
VS = ±18 V,
(V–) < VCM < (V+) – 3 V		 TA = –40°C to +125°C 114 126
VS = ±18 V,
(V+) – 1.5 V < VCM < (V+)		 96 120
TA = –40°C to +125°C 86 100
(V+) – 3 V < VCM < (V+) – 1.5 V See Typical Characteristics
INPUT IMPEDANCE
ZID Differential 100 || 1.6 MΩ || pF
ZIC Common-mode 1 || 6.4 1013Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = ±18 V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ		 124 134 dB
TA = –40°C to +125°C 114 126
VS = ±18 V,
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ		 126 140
TA = –40°C to +125°C 120 134
FREQUENCY RESPONSE
GBW Unity gain bandwidth 2.5 MHz
SR Slew rate VS = ±18 V, G = 1, 10-V step Rising 7.5 V/µs
Falling 5.5
ts Settling time To 0.01%, CL = 20 pF VS = ±18 V, G = 1, 2-V step 0.7 µs
VS = ±18 V, G = 1, 5-V step 1
To 0.001%, CL = 20 pF VS = ±18 V, G = 1, 2-V step 1.8
VS = ±18 V, G = 1, 5-V step 3.7
tOR Overload recovery time VIN × G = VS From overload to negative rail 0.4 µs
From overload to positive rail 1
THD+N Total harmonic distortion + noise G = 1, f = 1 kHz, VO = 3.5 VRMS 0.0012%
Crosstalk OPA2196 and OPA4196, at dc 150 dB
OPA2196 and OPA4196, f = 100 kHz 130 dB
OUTPUT
VO Voltage output swing from rail Positive rail No load 5 15 mV
RL = 10 kΩ 50 110
RL = 2 kΩ 200 500
Negative rail No load 5 15
RL = 10 kΩ 50 110
RL = 2 kΩ 200 500
ISC Short-circuit current VS = ±18 V ±65 mA
CL Capacitive load drive See Typical Characteristics
ZO Open-loop output impedance f = 1 MHz, IO = 0 A, See Figure 19 700 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 140 200 µA
TA = –40°C to +125°C 250
TEMPERATURE
Thermal protection 180 °C
Thermal hysteresis 30 °C

6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)

at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = ±2.25V,
VCM = (V+) – 3 V		 ±25 ±100 µV
(V+) – 3.0 V < VCM < (V+) – 1.5 V See Common-Mode Voltage Range
VS = ±3V,
VCM = (V+) – 1.5 V		 ±25 ±100
dVOS/dT Input offset voltage drift VS = ±2.25V, VCM = (V+) – 3 V TA = –40°C to +125°C ±0.5 µV/°C
VS = ±2.25V, VCM = (V+) – 1.5 V ±0.5
PSRR Power-supply rejection ratio TA = –40°C to +125°C, VCM = VS / 2 – 0.75 V ±1 µV/V
INPUT BIAS CURRENT
IB Input bias current ±5 ±20 pA
IOS Input offset current ±2 ±20 pA
NOISE
En Input voltage noise (V–) – 0.1 V < VCM < (V+) – 3 V f = 0.1 Hz to 10 Hz 1.4 µVPP
(V+) – 1.5 V < VCM < (V+) + 0.1 V f = 0.1 Hz to 10 Hz 7
en Input voltage noise density (V–) – 0.1 V < VCM < (V+) – 3 V f = 100 Hz 18 nV/√Hz
f = 1 kHz 15
(V+) – 1.5 V < VCM < (V+) + 0.1 V f = 100 Hz 53
f = 1 kHz 24
in Input current noise density f = 1 kHz 1.5 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage range (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio VS = ±2.25 V,
(V–) – 0.1 V < VCM < (V+) – 3 V		 96 110 dB
VS = ±2.25 V,
(V–) < VCM < (V+) – 3 V		 TA = –40°C to +125°C 90 104
VS = ±2.25 V,
(V+) – 1.5 V < VCM < (V+)		 96 120
TA = –40°C to +125°C 84 100
(V+) – 3 V < VCM < (V+) – 1.5 V See Typical Characteristics
INPUT IMPEDANCE
ZID Differential 100 || 1.6 MΩ || pF
ZIC Common-mode 1 || 6.4 1013Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = ±2.25V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ		 110 120 dB
TA = –40°C to +125°C 100 114
VS = ±2.25V,
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ		 110 126
TA = –40°C to +125°C 106 120
FREQUENCY RESPONSE
GBW Unity gain bandwidth 2.2 MHz
SR Slew rate VS = ±2.25V, G = 1, 1-V step Rising 6.5 V/µs
Falling 5.5
tOR Overload recovery time VIN × G = VS From overload to negative rail 0.4 µs
From overload to positive rail 1
Crosstalk OPA2196 and OPA4196, at dc 150 dB
OPA2196 and OPA4196, f = 100 kHz 130 dB
OUTPUT
VO Voltage output swing from rail Positive rail No load 5 15 mV
RL = 10 kΩ 15 110
RL = 2 kΩ 60 500
Negative rail No load 5 15
RL = 10 kΩ 15 110
RL = 2 kΩ 60 500
ISC Short-circuit current VS = ±2.25V ±30 mA
CL Capacitive load drive See Typical Characteristics
ZO Open-loop output impedance f = 1 MHz, IO = 0 A, see Figure 19 700 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 140 200 µA
TA = –40°C to +125°C 250
TEMPERATURE
Thermal protection 180 °C
Thermal hysteresis 30 °C

6.9 Typical Characteristics

Table 1. Table of Graphs

DESCRIPTION FIGURE
Offset Voltage vs Common-Mode Voltage Figure 1
Open-Loop Gain and Phase vs Frequency Figure 2
Closed-Loop Gain and Phase vs Frequency Figure 3
Input Bias Current vs Common-Mode Voltage Figure 4
Input Bias Current vs Temperature Figure 5
Output Voltage Swing vs Output Current (maximum supply) Figure 6, Figure 7
CMRR and PSRR vs Frequency Figure 8
CMRR vs Temperature Figure 9
PSRR vs Temperature Figure 10
0.1-Hz to 10-Hz Noise Figure 11
Input Voltage Noise Spectral Density vs Frequency Figure 12
THD+N Ratio vs Frequency Figure 13
THD+N vs Output Amplitude Figure 14
Quiescent Current vs Supply Voltage Figure 15
Quiescent Current vs Temperature Figure 16
Open Loop Gain vs Temperature Figure 17, Figure 18
Open Loop Output Impedance vs Frequency Figure 19
Small Signal Overshoot vs Capacitive Load (100-mV output step) Figure 20, Figure 21
No Phase Reversal Figure 22
Overload Recovery Figure 23
Small-Signal Step Response (100 mV) Figure 24, Figure 25
Large-Signal Step Response Figure 26, Figure 27
Settling Time Figure 28, Figure 29, Figure 30, Figure 31
Short-Circuit Current vs Temperature Figure 32
Maximum Output Voltage vs Frequency Figure 33
Propagation Delay Rising Edge Figure 34
Propagation Delay Falling Edge Figure 35
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
OPA196 OPA2196 OPA4196 C015_SBOS701.png
Figure 1. Offset Voltage vs Common-Mode Voltage
OPA196 OPA2196 OPA4196 C201_SBOS701.png
Figure 2. Open-Loop Gain and Phase vs Frequency
OPA196 OPA2196 OPA4196 C202_SBOS701.png
Figure 3. Closed-Loop Gain vs Frequency
OPA196 OPA2196 OPA4196 C002_SBOS701.png
Figure 5. Input Bias Current vs Temperature
OPA196 OPA2196 OPA4196 D020_SBOS701.gif
Sinking
Figure 7. Output Voltage Swing vs Output Current
OPA196 OPA2196 OPA4196 C011_SBOS701.png
Figure 9. CMRR vs Temperature
OPA196 OPA2196 OPA4196 C204_SBOS701.gif
Figure 11. 0.1-Hz to 10-Hz Noise
OPA196 OPA2196 OPA4196 C206_SBOS701.png
Figure 13. THD+N vs Frequency
OPA196 OPA2196 OPA4196 D021_SBOS701.gif
Figure 15. Quiescent Current vs Supply Voltage
OPA196 OPA2196 OPA4196 C001_10k_SBOS701.png
RL = 10 kΩ
Figure 17. Open-Loop Gain vs Temperature
OPA196 OPA2196 OPA4196 D017_SBOS701.gif
Figure 19. Open-Loop Output Impedance vs Frequency
OPA196 OPA2196 OPA4196 C209_SBOS701.png
G = 1, 100-mV output step
Figure 21. Small-Signal Overshoot vs Capacitive Load
OPA196 OPA2196 OPA4196 D014_SBOS701.gif
VS = ±18 V, G = –10 V/V
Figure 23. Overload Recovery
OPA196 OPA2196 OPA4196 C214_SBOS701.png
G = –1, RL = 1 kΩ, CL = 10 pF
Figure 25. Small-Signal Step Response
OPA196 OPA2196 OPA4196 C216_SBOS701.png
G = –1, RL = 1 kΩ, CL = 10 pF
Figure 27. Large-Signal Step Response
OPA196 OPA2196 OPA4196 D024_SBOS701.gif
Gain = 1, 2-V step, falling, step applied at t = 0 µs
Figure 29. 0.01% Settling Time
OPA196 OPA2196 OPA4196 D026_SBOS701.gif
Gain = 1, 5-V step, falling, step applied at t = 0 µs
Figure 31. 0.01% Settling Time
OPA196 OPA2196 OPA4196 C223_SBOS701.png
Figure 33. Maximum Output Voltage vs Frequency
OPA196 OPA2196 OPA4196 C221_SBOS701.png
Figure 35. Propagation Delay Falling Edge
OPA196 OPA2196 OPA4196 C003_SBOS701.png
Figure 4. Input Bias Current vs Common-Mode Voltage
OPA196 OPA2196 OPA4196 D019_SBOS701.gif
Sourcing
Figure 6. Output Voltage Swing vs Output Current
OPA196 OPA2196 OPA4196 C203_SBOS701.png
Figure 8. CMRR and PSRR vs Frequency
OPA196 OPA2196 OPA4196 C012_SBOS701.png
Figure 10. PSRR vs Temperature
OPA196 OPA2196 OPA4196 C205_SBOS701.png
Figure 12. Input Voltage Noise Spectral Density
vs Frequency
OPA196 OPA2196 OPA4196 D022_SBOS701.gif
Figure 14. THD+N vs Output Amplitude
OPA196 OPA2196 OPA4196 C004_SBOS701.png
Figure 16. Quiescent Current vs Temperature
OPA196 OPA2196 OPA4196 C001_2k_SBOS701.png
RL = 2 kΩ
Figure 18. Open-Loop Gain vs Temperature
OPA196 OPA2196 OPA4196 C208_SBOS701.png
G = –1, 100-mV output step
Figure 20. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
OPA196 OPA2196 OPA4196 D027_SBOS701.gif
Figure 22. No Phase Reversal
OPA196 OPA2196 OPA4196 C213_SBOS701.png
G = 1, CL = 10 pF
Figure 24. Small-Signal Step Response
OPA196 OPA2196 OPA4196 C215_SBOS701.png
G = 1, CL = 10 pF
Figure 26. Large-Signal Step Response
OPA196 OPA2196 OPA4196 D023_SBOS701.gif
Gain = 1, 2-V step, rising, step applied at t = 0 µs on all four plots
Figure 28. 0.01% Settling Time
OPA196 OPA2196 OPA4196 D025_SBOS701.gif
Gain = 1, 5-V step, rising, step applied at t = 0 µs
Figure 30. 0.01% Settling Time
OPA196 OPA2196 OPA4196 C006_SBOS701.png
Figure 32. Short-Circuit Current vs Temperature
OPA196 OPA2196 OPA4196 C222_SBOS701.png
Figure 34. Propagation Delay Rising Edge