JAJS198L
October 2006 – January 2020
OPA211
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
入力電圧ノイズ密度と周波数との関係
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Functions
Pin Functions: OPA211
Pin Functions: OPA2211
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information: OPA211 and OPA211A
7.5
Thermal Information: OPA2211 and OPA2211A
7.6
Electrical Characteristics: Standard Grade OPAx211A
7.7
Electrical Characteristics: High-Grade OPAx211
7.8
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Total Harmonic Distortion Measurements
8.4
Device Functional Modes
8.4.1
Shutdown
9
Application and Implementation
9.1
Application Information
9.1.1
Operating Voltage
9.1.2
Input Protection
9.1.3
Noise Performance
9.1.4
Basic Noise Calculations
9.1.5
EMI Rejection
9.1.6
EMIRR +IN Test Configuration
9.1.7
Electrical Overstress
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
SON Layout Guidelines
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
デバイス・サポート
12.1.1
開発サポート
12.1.1.1
TINA-TI™ (無料のダウンロード・ソフトウェア)
12.1.1.2
TI Precision Designs
12.1.1.3
WEBENCH® Filter Designer
12.2
ドキュメントのサポート
12.2.1
関連資料
12.3
関連リンク
12.4
ドキュメントの更新通知を受け取る方法
12.5
サポート・リソース
12.6
商標
12.7
静電気放電に関する注意事項
12.8
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
D|8
MSOI002K
DRG|8
MPDS151B
DGK|8
MPDS028E
サーマルパッド・メカニカル・データ
DRG|8
QFND128G
発注情報
jajs198l_oa
jajs198l_pm
7.8
Typical Characteristics
at T
A
= 25°C, V
S
= ±18 V, and R
L
= 10 kΩ, unless otherwise noted.
Figure 1.
Input Voltage Noise Density vs Frequency
Figure 3.
THD + N Ratio vs Frequency
Figure 5.
0.1- to 10-Hz Noise
Figure 7.
Common-Mode Rejection Ratio vs Frequency
Figure 9.
Gain and Phase vs Frequency
Figure 11.
Offset Voltage Production Distribution
Figure 13.
I
B
and I
OS
Current vs Temperature
Figure 15.
V
OS
Warm-Up
Figure 17.
Input Offset Current vs Common-Mode Voltage
Figure 19.
Input Bias Current vs Common-Mode Voltage
Figure 21.
Quiescent Current vs Supply Voltage
Figure 23.
Short-Circuit Current vs Temperature
(100 mV)
Figure 25.
Small-Signal Step Response
(100 mV)
Figure 27.
Small-Signal Step Response
Figure 29.
Large-Signal Step Response
10 V
PP
C
L
= 100 pF
Figure 31.
Large-Signal Positive Settling Time
10 V
PP
C
L
= 100 pF
Figure 33.
Large-Signal Negative Settling Time
Figure 35.
Negative Overload Recovery
Figure 37.
Output Voltage vs Output Current
Figure 39.
Turnoff Transient
Figure 41.
Turnon and Turnoff Transient
Figure 2.
Input Current Noise Density vs Frequency
Figure 4.
THD + N Ratio vs Output Voltage Amplitude
Figure 6.
Power-Supply Rejection Ratio vs Frequency (Referred to Input)
Figure 8.
Open-Loop Output Impedance vs Frequency
Figure 10.
Open-Loop Gain vs Temperature
Figure 12.
Offset Voltage Drift Production Distribution
Figure 14.
Offset Voltage vs Common-Mode Voltage
Figure 16.
Input Offset Current vs Supply Voltage
Figure 18.
Input Bias Current vs Supply Voltage
Figure 20.
Quiescent Current vs Temperature
Figure 22.
Normalized Quiescent Current vs Time
Figure 24.
Small-Signal Step Response (100 mV)
(100 mV)
Figure 26.
Small-Signal Step Response
(100-mV output step)
Figure 28.
Small-Signal Overshoot vs Capacitive Load
Figure 30.
Large-Signal Step Response
10 V
PP
C
L
= 10 pF
Figure 32.
Large-Signal Positive Settling Time
10 V
PP
C
L
= 10 pF
Figure 34.
Large-Signal Negative Settling Time
Figure 36.
Positive Overload Recovery
Figure 38.
No Phase Reversal
Figure 40.
Turnon Transient