JAJSMN6B November   1994  – July 2024 OPA131 , OPA2131 , OPA4131

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information - OPA131
    4. 5.4 Thermal Information - OPA2131
    5. 5.5 Thermal Information - OPA4131
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Offset Voltage Trim
    2. 6.2 Typical Application
      1. 6.2.1 Input Bias Current
  8. 7Device and Documentation Support
    1. 7.1 ドキュメントの更新通知を受け取る方法
    2. 7.2 サポート・リソース
    3. 7.3 Trademarks
    4. 7.4 静電気放電に関する注意事項
    5. 7.5 用語集
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

OPA131 OPA2131 OPA4131 OPA131 D Package, 8-Pin SOIC (Top View) Figure 4-1 OPA131 D Package, 8-Pin SOIC (Top View)
Table 4-1 Pin Functions: OPA131
PIN TYPE DESCRIPTION
NAME NO.
+IN 3 Input Noninverting input, channel A
–IN 2 Input Inverting input, channel A
NC 1, 5 — Do not connect these pins(1)
NC 8 — No internal connection. Float this pin.
OUT 6 Output Output
V+ 7 Power Positive (highest) power supply
V– 4 Power Negative (lowest) power supply
(1) Existing layouts for the OPA131 D package before revision B of this data sheet do not need to be redesigned.
OPA131 OPA2131 OPA4131 OPA2131 D Package, 8-Pin SOIC (Top View) Figure 4-2 OPA2131 D Package, 8-Pin SOIC (Top View)
Table 4-2 Pin Functions: OPA2131
PIN TYPE DESCRIPTION
NAME NO.
+IN A 3 Input Noninverting input, channel A
+IN B 5 Input Noninverting input, channel B
–IN A 2 Input Inverting input, channel A
–IN B 6 Input Inverting input, channel B
OUT A 1 Output Output, channel A
OUT B 7 Output Output, channel B
V+ 8 Power Positive (highest) power supply
V– 4 Power Negative (lowest) power supply
OPA131 OPA2131 OPA4131 OPA4131 D Package, 14-Pin SOIC, and N Package, 14-Pin PDIP (Top View) Figure 4-3 OPA4131 D Package, 14-Pin SOIC, and N Package, 14-Pin PDIP (Top View)
Table 4-3 Pin Functions: OPA4131 D and N packages
PIN TYPE DESCRIPTION
NAME NO.
+IN A 3 Input Noninverting input, channel A
+IN B 5 Input Noninverting input, channel B
+IN C 10 Input Noninverting input, channel C
+IN D 12 Input Noninverting input, channel D
–IN A 2 Input Inverting input, channel A
–IN B 6 Input Inverting input, channel B
–IN C 9 Input Inverting input, channel C
–IN D 13 Input Inverting input, channel D
OUT A 1 Output Output, channel A
OUT B 7 Output Output, channel B
OUT C 8 Output Output, channel C
OUT D 14 Output Output, channel D
V+ 4 Power Positive (highest) power supply
V– 11 Power Negative (lowest) power supply
Figure 4-4 OPA4131 DW Package, 16-Pin SOIC (Top View)
Table 4-4 Pin Functions: OPA4131 DW Package
PIN TYPE DESCRIPTION
NAME NO.
+IN A 3 Input Noninverting input, channel A
+IN B 5 Input Noninverting input, channel B
+IN C 12 Input Noninverting input, channel C
+IN D 14 Input Noninverting input, channel D
–IN A 2 Input Inverting input, channel A
–IN B 6 Input Inverting input, channel B
–IN C 11 Input Inverting input, channel C
–IN D 15 Input Inverting input, channel D
OUT A 1 Output Output, channel A
OUT B 7 Output Output, channel B
OUT C 10 Output Output, channel C
OUT D 16 Output Output, channel D
V+ 4 Power Positive (highest) power supply
V– 13 Power Negative (lowest) power supply
NC 8, 9 — No internal connection. Float this pin.