JAJSV75C January   1995  – August 2024 OPA132 , OPA2132 , OPA4132

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information - OPA132
    5. 5.5 Thermal Information - OPA2132
    6. 5.6 Thermal Information - OPA4132
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Operating Voltage
      2. 7.1.2 Offset Voltage Trim
      3. 7.1.3 Input Bias Current
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Analog Filter Designer
        2. 8.1.1.2 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
        3. 8.1.1.3 TI のリファレンス・デザイン
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.7 Electrical Characteristics

at TA = 25°C, VS = ±15V, RL = 2kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage    OPAx132U ±0.2 ±0.5 mV
OPAx132UA ±0.5 ±2
dVOS/dT Input offset voltage drift TA = –40°C to +85°C ±2 ±10 μV/°C
PSRR Power-supply rejection ratio  ±2.5V ≤ VS ≤ ±18V OPAx132U ±5 ±15 μV/V
OPAx132UA ±5 ±30
Channel separation (dual and quad) RL = 2kΩ 0.2 μV/V
INPUT BIAS CURRENT
IB Input bias current(1) ±5 ±50 pA
TA = –40°C to +85°C See Typical Characteristics
IOS Input offset current(1) ±2 ±50 pA
NOISE
en Input voltage noise density f = 10Hz 23 nV/√Hz
f = 100Hz 10
f = 1kHz 8
f = 10kHz 8
In Input current noise density f = 1kHz 3 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage (V–) + 2.5 ±13 (V+) – 3.5 V
CMRR Common-mode rejection ratio –12.5V ≤ VCM ≤ 11.5V  OPAx132U 96 100 dB
OPAx132UA 86 94
INPUT IMPEDANCE
Differential   1013 || 10 Ω || pF
Common-mode –12.5V ≤ VCM ≤ 11.5V 1013 || 7
OPEN-LOOP GAIN
AOL Open-loop voltage gain RL = 10kΩ,
–14.5V ≤ VO ≤ 13.8V		 OPAx132U 110 120 dB
OPAx132UA 104 120
RL = 2kΩ,
–13.8V ≤ VO ≤ 13.5V		 OPAx132U 110 126
OPAx132UA 104 120
RL = 600Ω,
–12.8V ≤ VO ≤ 12.5V		 OPAx132U 110 130
OPAx132UA 104 120
FREQUENCY RESPONSE
GBW Gain bandwidth product 8 MHz
SR Slew rate ±20 V/μs
Settling time  10V step, G = 1, CL = 100pF 0.1% 0.7 μs
0.01% 1
THD+N Total harmonic distortion plus noise f = 1kHz, G = 1, VO = 3.5Vrms RL = 2kΩ 0.0008%
RL = 600Ω 0.0009%
Overload recovery time  G = ±1  600 ns
OUTPUT
VO Voltage output  RL = 10kΩ Positive (V+) – 1.2 (V+) – 0.9 V
Negative (V–) + 0.3 (V–) + 0.5
RL = 2kΩ Positive (V+) – 1.5 (V+) – 1.1
Negative (V–) + 1.2 (V–) + 0.9
RL = 600Ω Positive (V+) – 2.5 (V+) – 2.0
Negative (V–) + 2.2 (V–) + 1.5
ISC Short-circuit current Sourcing 36 mA
Sinking –30 mA
Capacitive load drive (stable operation) See Typical Characteristics
POWER SUPPLY
IQ Quiescent current (per amplifier)  IO = 0mA  ±4 ±4.8 mA
(1) High-speed test at TJ = 25°C.