JAJSCN7A November   2016  – June 2017 OPA2172-Q1 , OPA4172-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 EMI Rejection
      2. 8.3.2 Phase-Reversal Protection
      3. 8.3.3 Capacitive Load and Stability
    4. 8.4 Device Functional Modes
      1. 8.4.1 Common-Mode Voltage Range
      2. 8.4.2 Electrical Overstress
      3. 8.4.3 Overload Recovery
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Bidirectional Current Source
      3. 9.2.3 JFET-Input Low-Noise Amplifier
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 TINA-TI(無料のダウンロード・ソフトウェア)
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage Supply voltage, V+ to V– –20 20 V
Single-supply voltage 40
Signal input pins voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5
Differential(4) –0.5 0.5
Current Signal input pins current –10 10 mA
Output short-circuit(3) Continuous
Temperature Junction, TJ 150 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transient conditions that exceed these voltage ratings must be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
(4) Refer to the Electrical Overstress section for more information.

7.2 ESD Ratings

VALUE UNIT
OPA2172-Q1 in DGK package
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V
Charged-device model (CDM), per AEC Q100-011 ±1000
OPA4172-Q1 in PW package
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V
Charged-device model (CDM), per AEC Q100-011 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage, (V+) – (V–) Single-supply 4.5 36 V
Dual-supply ±2.25 ±18
Specified temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) OPA2172-Q1 OPA4172-Q1 UNIT
DGK (VSSOP) PW (TSSOP)
8 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 181.4 107.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 69.2 32.5 °C/W
RθJB Junction-to-board thermal resistance 103.3 50.4 °C/W
ψJT Junction-to-top characterization parameter 10.9 1.8 °C/W
ψJB Junction-to-board characterization parameter 101.6 49.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±0.2 ±1 mV
TA = –40°C to +125°C ±1.15
dVOS/dT Input offset voltage drift TA = –40°C to +125°C OPA4172-Q1 ±0.3 ±1.5 µV/°C
OPA2172-Q1 ±1.8
PSRR Power-supply rejection ratio TA = –40°C to +125°C ±1 ±3 µV/V
Channel separation, dc At dc 5 µV/V
INPUT BIAS CURRENT
IB Input bias current TA = 25°C ±8 ±15 pA
TA = –40°C to +125°C OPA2172-Q1IDGK ±18 nA
OPA4172-Q11PW
IOS Input offset current TA = 25°C ±2 ±15 pA
TA = –40°C to +125°C OPA4172-Q1 ±1 nA
OPA2172-Q1 ±3
NOISE
En Input voltage noise f = 0.1 Hz to 10 Hz 2 µVPP
en Input voltage noise density f = 100 Hz 12 nV/√Hz
f = 1 kHz 7
in Input current noise density f = 1 kHz 1.6 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage(1) (V–) – 0.1 V (V+) – 2 V V
CMRR Common-mode rejection ratio VS = ±2.25 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C		 90 104 dB
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C		 110 120
INPUT IMPEDANCE
Differential 100 || 4 MΩ || pF
Common-mode 6 || 4 1013Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.35 V < VO < (V+) – 0.35 V, RL = 10 kΩ, TA = –40°C to +125°C OPA4172-Q1 110 130 dB
OPA2172-Q1 107 115
(V–) + 0.5 V < VO < (V+) – 0.5 V,
RL = 2 kΩ, TA = –40°C to +125°C		 OPA4172-Q1 116
OPA2172-Q1 107
FREQUENCY RESPONSE
GBP Gain bandwidth product 10 MHz
SR Slew rate G = 1 10 V/µs
tS Settling time To 0.1%, VS = ±18 V, G = 1, 10-V step 2 µs
To 0.01% (12 bit), VS = ±18 V, G = 1, 10-V step 3.2
Overload recovery time VIN × Gain > VS 200 ns
THD+N Total harmonic distortion + noise VS = 36 V, G = 1, f = 1 kHz, VO = 3.5 VRMS 0.00005%
OUTPUT
VO Voltage output swing from rail VS = +36 V RL = 10 kΩ 70 90 mV
RL = 2 kΩ 330 400
VS = +36 V,
TA = –40°C to +125°C		 RL = 10 kΩ 95 120
RL = 2 kΩ 470 530
VS = 4.5 V RL = 10 kΩ 10 20
RL = 2 kΩ 40 50
VS = 4.5 V,
TA = –40°C to +125°C		 RL = 10 kΩ 10 25
RL = 2 kΩ 55 70
ISC Short-circuit current ±75 mA
CLOAD Capacitive load drive See the Typical Characteristics pF
ZO Open-loop output impedance f = 1 MHz, IO = 0 A 60 Ω
POWER SUPPLY
VS Specified voltage 4.5 36 V
IQ Quiescent current per amplifier IO = 0 A 1.6 1.8 mA
IO = 0 A, TA = –40°C to +125°C 2
(1) The input range can be extended beyond (V+) – 2 V up to (V+) + 0.1 V. See the Typical Characteristics and Application Information sections for additional information.

7.6 Typical Characteristics

at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
OPA2172-Q1 OPA4172-Q1 C016_OT_SBOS618.png
Figure 1. Offset Voltage Production Distribution
OPA2172-Q1 OPA4172-Q1 C001_OT_SBOS618.png
Figure 3. Offset Voltage vs Temperature
(VS = ±18 V)
OPA2172-Q1 OPA4172-Q1 C017_OT_SBOS618.png
Figure 5. Offset Voltage vs Common-Mode Voltage
(Upper Stage)
OPA2172-Q1 OPA4172-Q1 C013_OT_SBOS618.png
Figure 7. Input Bias Current vs Common-Mode Voltage
OPA2172-Q1 OPA4172-Q1 C011_OT_SBOS618.png
Figure 9. Output Voltage Swing vs Output Current (Maximum Supply)
OPA2172-Q1 OPA4172-Q1 C007_OT_SBOS618.png
Figure 11. CMRR vs Temperature
OPA2172-Q1 OPA4172-Q1 C001_SBOS809.png
Figure 13. 0.1-Hz to 10-Hz Noise
OPA2172-Q1 OPA4172-Q1 C008_SBOS618.png
Figure 15. THD+N Ratio vs Frequency
OPA2172-Q1 OPA4172-Q1 C009_OT_SBOS618.png
Figure 17. Quiescent Current vs Temperature
OPA2172-Q1 OPA4172-Q1 C004_SBOS618.png
Figure 19. Open-Loop Gain and Phase vs Frequency
OPA2172-Q1 OPA4172-Q1 C008_OT_SBOS618.png
Figure 21. Open-Loop Gain vs Temperature
OPA2172-Q1 OPA4172-Q1 C022_SBOS809.gif
Figure 23. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
OPA2172-Q1 OPA4172-Q1 C011_SBOS809.gif
Figure 25. Positive Overload Recovery
OPA2172-Q1 OPA4172-Q1 C013_SBOS809.gif
Figure 27. Negative Overload Recovery
OPA2172-Q1 OPA4172-Q1 C007_SBOS809.gif
Figure 29. Small-Signal Step Response (10 mV, G = –1)
OPA2172-Q1 OPA4172-Q1 C006_SBOS809.gif
Figure 31. Small-Signal Step Response (100 mV, G = –1)
OPA2172-Q1 OPA4172-Q1 C005_SBOS809.gif
Figure 33. Large-Signal Step Response (10 V, G = –1)
OPA2172-Q1 OPA4172-Q1 C024_SBOS618.png
Figure 35. Large-Signal Settling Time (10-V Positive Step)
OPA2172-Q1 OPA4172-Q1 C014_SBOS809.gif
Figure 37. No Phase Reversal
OPA2172-Q1 OPA4172-Q1 C023_SBOS618.png
Figure 39. Maximum Output Voltage vs Frequency
OPA2172-Q1 OPA4172-Q1 C041_SBOS618.png
Figure 41. Channel Separation vs Frequency
OPA2172-Q1 OPA4172-Q1 C015_OT_SBOS618.png
Figure 2. Offset Voltage Drift Production Distribution
OPA2172-Q1 OPA4172-Q1 C002_OT_SBOS618.png
Figure 4. Offset Voltage vs Common-Mode Voltage
(VS = ±18 V)
OPA2172-Q1 OPA4172-Q1 C005_OT_SBOS618.png
Figure 6. Offset Voltage vs Power Supply
OPA2172-Q1 OPA4172-Q1 C012_OT_SBOS618.png
Figure 8. Input Bias Current vs Temperature
OPA2172-Q1 OPA4172-Q1 C015_SBOS618.png
Figure 10. CMRR and PSRR vs Frequency
(Referred-to-Input)
OPA2172-Q1 OPA4172-Q1 C006_OT_SBOS618.png
Figure 12. PSRR vs Temperature
OPA2172-Q1 OPA4172-Q1 C002_SBOS618.png
Figure 14. Input Voltage Noise Spectral Density vs Frequency
OPA2172-Q1 OPA4172-Q1 C009_SBOS618.png
Figure 16. THD+N vs Output Amplitude
OPA2172-Q1 OPA4172-Q1 C010_OT_SBOS618.png
Figure 18. Quiescent Current vs Supply Voltage
OPA2172-Q1 OPA4172-Q1 C003_SBOS618.png
Figure 20. Closed-Loop Gain vs Frequency
OPA2172-Q1 OPA4172-Q1 C019_SBOS809.gif
Figure 22. Open-Loop Output Impedance vs Frequency
OPA2172-Q1 OPA4172-Q1 C021_SBOS809.gif
Figure 24. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
OPA2172-Q1 OPA4172-Q1 C010_SBOS809.gif
Figure 26. Positive Overload Recovery (Zoomed In)
OPA2172-Q1 OPA4172-Q1 C012_SBOS809.gif
Figure 28. Negative Overload Recovery (Zoomed In)
OPA2172-Q1 OPA4172-Q1 C018_SBOS809.gif
Figure 30. Small-Signal Step Response (10 mV, G = 1)
OPA2172-Q1 OPA4172-Q1 C017_SBOS809.gif
Figure 32. Small-Signal Step Response (100 mV, G = 1)
OPA2172-Q1 OPA4172-Q1 C016_SBOS809.gif
Figure 34. Large-Signal Step Response (10 V, G = 1)
OPA2172-Q1 OPA4172-Q1 C025_SBOS618.png
Figure 36. Large-Signal Settling Time (10-V Negative Step)
OPA2172-Q1 OPA4172-Q1 C014_OT_SBOS618.png
Figure 38. Short-Circuit Current vs Temperature
OPA2172-Q1 OPA4172-Q1 C020_SBOS618.png
Figure 40. EMIRR vs Frequency