JAJSNV3C june   2022  – july 2023 OPA186 , OPA2186 , OPA4186

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA186
    5. 6.5 Thermal Information: OPA2186
    6. 6.6 Thermal Information: OPA4186
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Rail-to-Rail Inputs
      2. 7.3.2 Phase-Reversal Protection
      3. 7.3.3 Input Bias Current Clock Feedthrough
      4. 7.3.4 EMI Rejection
        1. 7.3.4.1 EMIRR +IN Test Configuration
      5. 7.3.5 Electrical Overstress
      6. 7.3.6 MUX-Friendly Inputs
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Noise Calculations
    2. 8.2 Typical Applications
      1. 8.2.1 High-Side Current Sensing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Bridge Amplifier
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristics

at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)

Table 6-1 Typical Characteristic Graphs
DESCRIPTIONFIGURE
Offset Voltage DistributionFigure 6-1
Offset Voltage Drift (-40°C to +125C°C)Figure 6-2
Input Bias Current DistributionFigure 6-3
Input Offset Current DistributionFigure 6-4
Offset Voltage vs Common-Mode VoltageFigure 6-5
Offset Voltage vs Supply VoltageFigure 6-6
Input Bias Current vs Common-Mode Voltage Figure 6-7
Open-Loop Gain and Phase vs FrequencyFigure 6-8
Closed-Loop Gain vs FrequencyFigure 6-9
Input Bias Current and Offset Current vs TemperatureFigure 6-10
Output Voltage Swing vs Output Current (Sourcing)Figure 6-11
Output Voltage Swing vs Output Current (Sinking)Figure 6-12
CMRR and PSRR vs FrequencyFigure 6-13
CMRR vs TemperatureFigure 6-14
PSRR vs TemperatureFigure 6-15
0.1-Hz to 10-Hz Voltage NoiseFigure 6-16
Input Voltage Noise Spectral Density vs FrequencyFigure 6-17
THD+N vs FrequencyFigure 6-18
THD+N vs Output AmplitudeFigure 6-19
Quiescent Current vs Supply VoltageFigure 6-20
Quiescent Current vs TemperatureFigure 6-21
Open-Loop Gain vs Temperature (10 kΩ)Figure 6-22
Open-Loop Gain vs Temperature (2 kΩ)Figure 6-23
Open-Loop Output Impedance vs FrequencyFigure 6-24
Small-Signal Overshoot vs Capacitive Load (Gain = –1, 10-mV step)Figure 6-25
Small-Signal Overshoot vs Capacitive Load (Gain = 1, 10-mV step)Figure 6-26
No Phase ReversalFigure 6-27
Positive Overload RecoveryFigure 6-28
Negative Overload RecoveryFigure 6-29
Small-Signal Step Response (Gain = 1, 10-mV step)Figure 6-30
Small-Signal Step Response (Gain = –1, 10-mV step)Figure 6-31
Large-Signal Step Response (Gain = 1, 10-V step)Figure 6-32
Large-Signal Step Response (Gain = –1, 10-V step)Figure 6-33
Phase Margin vs Capacitive LoadFigure 6-34
Settling Time (1-V Step, 0.1% Settling)Figure 6-35
Short Circuit Current vs TemperatureFigure 6-36
Maximum Output Voltage vs FrequencyFigure 6-37
EMIRR vs FrequencyFigure 6-38
Channel SeparationFigure 6-39
GUID-20220825-SS0I-FNTS-SFZ4-7CTWRJWSTQGS-low.svg
 
Figure 6-1 Offset Voltage Distribution
GUID-20220825-SS0I-P3S4-Z5ZS-NGWDGP1L7WRM-low.svg
 
Figure 6-3 Input Bias Current Distribution
GUID-20220825-SS0I-KX44-1Q7H-GS3FRD9WBTLR-low.svg
 
Figure 6-5 Offset Voltage vs Common-Mode Voltage
GUID-20220825-SS0I-TJGK-XXGW-XXRRTBCB632H-low.svg
 
Figure 6-7 Input Bias Current vs Common-Mode Voltage
GUID-CB8D1E5D-732F-4848-AB6F-EBBEA582DE6F-low.gif
 
Figure 6-9 Closed-Loop Gain vs Frequency
GUID-F93245B6-92FF-4127-BB0C-B843C77D0756-low.gif
 
Figure 6-11 Output Voltage Swing vs
Output Current (Sourcing)
GUID-2EFD73F7-8498-4FFF-918A-2B8647B23E7C-low.gif
 
Figure 6-13 CMRR and PSRR vs Frequency
GUID-20220825-SS0I-P3QL-KQNJ-QSNFD2LLFDMV-low.svg
 
Figure 6-15 PSRR vs Temperature
GUID-0518DECC-BFEA-46A3-B71A-0703272ECA0D-low.gif
 
Figure 6-17 Input Voltage Noise Spectral Density vs Frequency
GUID-48C169B9-109F-4BE4-A1C0-022DBA1D3739-low.gif
 
Figure 6-19 THD+N vs Output Amplitude
GUID-4EE16E69-7316-4209-A79B-DF2ACAEF6D2C-low.gif
 
Figure 6-21 Quiescent Current vs Temperature
GUID-DF50FA95-64E3-4A43-BCBC-0DDC733FBBE0-low.gif
RL = 2 kΩ
Figure 6-23 Open-Loop Gain vs Temperature
GUID-B07A6801-DFA6-4512-ABEC-88FAB9F6436A-low.gif
Gain = –1, 10-mV step
Figure 6-25 Small-Signal Overshoot vs
Capacitive Load
GUID-70CA2719-6B28-4B81-91ED-2782A0A1399E-low.gif
 
Figure 6-27 No Phase Reversal
GUID-4A184C9E-7376-44C5-8BCA-B24A5815B237-low.gif
 
Figure 6-29 Negative Overload Recovery
GUID-B463EA34-C7E2-4FC5-B25A-9CE3AABB8FEA-low.gif
Gain = –1, 10-mV step
Figure 6-31 Small-Signal Step Response
GUID-918CDBA1-5093-49AB-8CA7-E7A25FF8B195-low.gif
Gain = –1, 10-V step
Figure 6-33 Large-Signal Step Response
GUID-0953CF08-D5F5-4EF9-A3B7-F8A996E663CD-low.gif
1-V step, 0.1% settling
Figure 6-35 Settling Time
GUID-48C60575-6BC6-4BE9-847D-D4C9427455A1-low.gif
 
Figure 6-37 Maximum Output Voltage vs Frequency
GUID-BE4BDE67-FB14-427F-B7D1-6D5686784765-low.gif
 
Figure 6-39 Channel Separation
GUID-20220825-SS0I-JZRN-RCSL-RDX04RQJQMDM-low.svg
 
Figure 6-2 Offset Voltage Drift (-40°C to 125C°C)
GUID-20220825-SS0I-RDHG-MJSK-HPRS6NDXQDVL-low.svg
 
Figure 6-4 Input Offset Current Distribution
GUID-20220825-SS0I-MLGM-94TV-PM4RCZQDB5PW-low.svg
 
Figure 6-6 Offset Voltage vs Supply Voltage
GUID-3DBE1B33-AE6B-47C9-B9B6-2A9C5E12E441-low.gif
 
 
Figure 6-8 Open-Loop Gain and Phase vs Frequency
GUID-20220825-SS0I-7ZGL-FR1K-NJGXTZFCXTGJ-low.svg
 
Figure 6-10 Input Bias Current and Offset Current vs Temperature
GUID-D1B4A4BA-AEA8-4E14-94C4-93F8F979742A-low.gif
 
Figure 6-12 Output Voltage Swing vs
Output Current (Sinking)
GUID-20220825-SS0I-KN8F-HJFR-CGSRCPXBZ34N-low.svg
 
Figure 6-14 CMRR vs Temperature
GUID-DA2404DA-A3AE-493D-9F83-B79D44733198-low.gif
 
Figure 6-16 0.1-Hz to 10-Hz Voltage Noise
GUID-38F19090-7BAA-4364-84A5-0C08FF5D30D8-low.gif
 
Figure 6-18 THD+N vs Frequency
GUID-C186F76A-593D-4702-AE0B-361881EBA0FC-low.gif
 
Figure 6-20 Quiescent Current vs Supply Voltage
GUID-5217815E-DA14-4B7A-BB63-CB9573CF684F-low.gif
 
Figure 6-22 Open-Loop Gain vs Temperature
GUID-2F285505-C05D-4ACC-831C-9857AE63FEF7-low.gif
 
Figure 6-24 Open-Loop Output Impedance vs Frequency
GUID-2A2D07C4-1D75-42E1-97E5-A6B582D2599D-low.gif
Gain = 1, 10-mV step
Figure 6-26 Small-Signal Overshoot vs
Capacitive Load
GUID-55B131C3-9396-4F8A-A7AD-9966238556F3-low.gif
 
Figure 6-28 Positive Overload Recovery
GUID-25041D00-E23D-4D1D-AD62-B4FC1E715D89-low.gif
Gain = 1, 10-mV step
Figure 6-30 Small-Signal Step Response
GUID-F9AC17A1-6A0F-4DAF-8A63-237E7ED8E2DE-low.gif
Gain = 1, 10-V step
Figure 6-32 Large-Signal Step Response
GUID-1FC8097D-FC60-4A75-8204-BB8278001C9F-low.gif
 
Figure 6-34 Phase Margin vs Capacitive Load
GUID-1EA1F64B-0F7F-48BA-8A4B-D2800D2E52B2-low.gif
 
Figure 6-36 Short Circuit Current vs Temperature
GUID-E911983F-FA64-47E3-AD03-6266D14BB8D6-low.gif
 
Figure 6-38 EMIRR vs Frequency