at TA = 25°C,
VS = ±15 V, RL = 10 kΩ connected to midsupply, and
VCM = VOUT = midsupply (unless otherwise noted)
Figure 6-1 Offset Voltage Production Distribution
Figure 6-3 Input Voltage Noise Spectral Density vs Frequency
Figure 6-5 0.1-Hz to 10-Hz Voltage Noise
Figure 6-7 THD+N
vs Output Amplitude
Figure 6-9 Offset Voltage vs Common-Mode Voltage
Figure 6-11 PSSR
vs Frequency
Figure 6-13 CMRR
vs Frequency
Figure 6-15 Open-Loop Output Impedance vs Frequency
Figure 6-17 Open-Loop Gain vs Temperature
Figure 6-19 Negative Input Bias Current Production Distribution
Figure 6-21 Input Bias and Input Offset Currents vs Temperature
Figure 6-23 Negative Input Bias Current vs Common-Mode Voltage
Figure 6-25 Quiescent Current vs Supply Voltage
Figure 6-27 Output Voltage vs Output Current (Sourcing)
Figure 6-29 Short-Circuit Current vs Temperature
Figure 6-31 Positive Overload Recovery![Small-Signal Step Response GUID-73E64C48-D196-48FC-90AC-9764BDA5BD6E-low.gif](/ods/images/JAJSG49H/GUID-73E64C48-D196-48FC-90AC-9764BDA5BD6E-low.gif)
G = +1 | 10-mV step, CL = 100 pF, RL = 600 Ω |
Figure 6-33 Small-Signal Step Response![Large-Signal Step Response GUID-BC401D92-8EE9-424C-983E-15EF8BDB5BE9-low.gif](/ods/images/JAJSG49H/GUID-BC401D92-8EE9-424C-983E-15EF8BDB5BE9-low.gif)
G = +1 | 10-V step, CL = 100 pF, RL = 600 Ω |
Figure 6-35 Large-Signal Step Response
Figure 6-37 Small-Signal Overshoot vs Capacitive Load
Figure 6-39 EMIRR vs Frequency
Figure 6-2 Offset Voltage Drift Distribution
Figure 6-4 Input Current Noise Spectral Density vs Frequency![THD+N Ratio vs Frequency GUID-142BF09E-D00B-484E-B52D-F6B10B8E0792-low.gif](/ods/images/JAJSG49H/GUID-142BF09E-D00B-484E-B52D-F6B10B8E0792-low.gif)
VOUT = 3.5 VRMS | RL = 600 Ω | |
| | |
Figure 6-6 THD+N Ratio vs Frequency
Figure 6-8 Input
Offset Voltage vs Temperature
Figure 6-10 Offset Voltage vs Supply Voltage
Figure 6-12 PSRR
vs Temperature
Figure 6-14 CMRR
vs Temperature
Figure 6-16 Open-Loop Gain and Phase vs Frequency
Figure 6-18 Positive Input Bias Current Production Distribution
Figure 6-20 Input Offset Current Production Distribution
Figure 6-22 Positive Input Bias Current vs Common-Mode Voltage
Figure 6-24 Input Offset Current vs Common-Mode Voltage
Figure 6-26 Quiescent Current vs Temperature
Figure 6-28 Output Voltage vs Output Current (Sinking)
Figure 6-30 No Phase Reversal
Figure 6-32 Negative Overload Recovery![Small-Signal Step Response GUID-D410A843-F661-4701-945E-B9B0A6E95FF4-low.gif](/ods/images/JAJSG49H/GUID-D410A843-F661-4701-945E-B9B0A6E95FF4-low.gif)
G = –1 | 10-mV step, CL = 100 pF, RL = 600 Ω |
Figure 6-34 Small-Signal Step Response![Large-Signal Step Response GUID-5DDEC94E-0839-475D-AA20-60D78EF661ED-low.gif](/ods/images/JAJSG49H/GUID-5DDEC94E-0839-475D-AA20-60D78EF661ED-low.gif)
G = –1 | 10-V step, CL = 100 pF, RL = 600 Ω |
Figure 6-36 Large-Signal Step Response
Figure 6-38 Settling Time