SBOS563G May   2011  – June 2015 OPA2314 , OPA314 , OPA4314

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA314
    5. 6.5 Thermal Information: OPA2314
    6. 6.6 Thermal Information: OPA4314
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Rail-to-Rail Input
      3. 7.3.3 Input and ESD Protection
      4. 7.3.4 Common-Mode Rejection Ratio (CMRR)
      5. 7.3.5 EMI Susceptibility and Input Filtering
      6. 7.3.6 Rail-to-Rail Output
      7. 7.3.7 Capacitive Load and Stability
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Configurations
      2. 8.1.2 Capacitive Load and Stability
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Amplifier Selection
        2. 8.2.2.2 Passive Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 DFN Package
    2. 11.2 Related Links
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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発注情報

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range, unless otherwise noted.(1)
MIN MAX UNIT
Supply voltage 7 V
Signal input terminals Voltage(2) (V–) – 0.5 (V+) + 0.5 V
Current(2) –10 10 mA
Output short-circuit(3) Continuous mA
Operating temperature, TA –40 150 °C
Junction temperature, TJ °C
Storage temperature, Tstg –65 150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS Supply voltage 1.8 (±0.9) 5.5 (±2.75) V
TA Ambient operating temperature –40 125 °C

6.4 Thermal Information: OPA314

THERMAL METRIC(1) OPA314 UNIT
DBV (SOT23) DCK (SC70) DRL (SOT553)
5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 228.5 281.4 208.1 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 99.1 91.6 0.1 °C/W
RθJB Junction-to-board thermal resistance 54.6 59.6 42.4 °C/W
ψJT Junction-to-top characterization parameter 7.7 1.5 0.5 °C/W
ψJB Junction-to-board characterization parameter 53.8 58.8 42.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Thermal Information: OPA2314

THERMAL METRIC(1) OPA2314 UNIT
D (SO) DGK (MSOP) DRB (DFN)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 138.4 191.2 53.8 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 89.5 61.9 69.2 °C/W
RθJB Junction-to-board thermal resistance 78.6 111.9 20.1 °C/W
ψJT Junction-to-top characterization parameter 29.9 5.1 3.8 °C/W
ψJB Junction-to-board characterization parameter 78.1 110.2 11.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Thermal Information: OPA4314

THERMAL METRIC(1) OPA4314 UNIT
D (SOIC) PW (TSSOP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 93.2 121 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 51.8 49.4 °C/W
RθJB Junction-to-board thermal resistance 49.4 62.8 °C/W
ψJT Junction-to-top characterization parameter 13.5 5.9 °C/W
ψJB Junction-to-board characterization parameter 42.2 62.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.7 Electrical Characteristics

VS = 1.8 V to 5.5 V; At TA = 25 °C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.(1)
PARAMETER TEST CONDITIONS TA = 25 °C TA = –40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX
OFFSET VOLTAGE
VOS Input offset voltage VCM = (VS+) – 1.3 V 0.5 2.5 mV
dVOS/dT vs Temperature 1 μV/°C
PSRR vs power supply VCM = (VS+) – 1.3 V 78 92 dB
Over temperature 74 dB
Channel separation, DC At DC 10 µV/V
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio VS = 1.8 V to 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V 75 96 dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V(2) 66 80 dB
Over temperature VS = 1.8 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V 70 86 dB
VS = 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V 73 90 dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V(2) 60 dB
INPUT BIAS CURRENT
IB Input bias current ±0.2 ±10 pA
Over temperature ±600 pA
IOS Input offset current ±0.2 ±10 pA
Over temperature ±600 pA
NOISE
Input voltage noise (peak-to-peak) f = 0.1 Hz to 10 Hz 5 μVPP
en Input voltage noise density f = 10 kHz 13 nV/√Hz
f = 1 kHz 14 nV/√Hz
in Input current noise density f = 1 kHz 5 fA/√Hz
INPUT CAPACITANCE
CIN Differential VS = 5 V 1 pF
Common-mode VS = 5 V 5 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 1.8 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ 90 115 dB
VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ 100 128 dB
VS = 1.8 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ(2) 90 100 dB
VS = 5.5 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ(2) 94 110 dB
Over temperature VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ 90 110 dB
VS = 5.5 V, 0.5 V < VO < (V+) – 0.2 V, RL = 2 kΩ 100 dB
Phase margin VS = 5 V, G = 1, RL = 10 kΩ 65 °
FREQUENCY RESPONSE
GBW Gain-bandwidth product VS = 1.8 V, RL = 10 kΩ, CL = 10 pF 2.7 MHz
VS = 5 V, RL = 10 kΩ, CL = 10 pF 3 MHz
SR Slew rate(3) VS = 5 V, G = 1 1.5 V/μs
tS Settling time To 0.1%, VS = 5 V, 2-V step , G = 1 2.3 μs
To 0.01%, VS = 5 V, 2-V step , G = 1 3.1 μs
Overload recovery time VS = 5 V, VIN  × Gain > VS 5.2 μs
THD+N Total harmonic distortion + noise(4) VS = 5 V, VO = 1 VRMS, G = +1, f = 1 kHz, RL = 10 kΩ 0.001%
OUTPUT
VO Voltage output swing from supply rails VS = 1.8 V, RL = 10 kΩ 5 15 mV
VS = 5.5 V, RL = 10 kΩ 5 20 mV
VS = 1.8 V, RL = 2 kΩ 15 30 mV
VS = 5.5 V, RL = 2 kΩ 22 40 mV
Over temperature VS = 5.5 V, RL = 10 kΩ 30 mV
VS = 5.5 V, RL = 2 kΩ 60 mV
ISC Short-circuit current VS = 5 V ±20 mA
RO Open-loop output impedance VS = 5.5 V, f = 100 Hz 570 Ω
POWER SUPPLY
VS Specified voltage range 1.8 5.5 V
IQ Quiescent current per amplifier OPA314, OPA2314, OPA4314, VS = 1.8 V, IO = 0 mA 130 180 µA
OPA2314, OPA4314, VS = 5 V, IO = 0 mA 150 190 µA
OPA314, VS = 5 V, IO = 0 mA 150 210 µA
Over temperature VS = 5 V, IO = 0 mA 220 µA
Power-on time VS = 0 V to 5 V, to 90% IQ level 44 µs
TEMPERATURE
Specified range –40 125 °C
Operating range –40 150 °C
Storage range –65 150 °C
(1) Parameters with minimum or maximum specification limits are 100% production tested at +25ºC, unless otherwise noted. Over temperature limits are based on characterization and statistical analysis.
(2) Specified by design and characterization; not production tested.
(3) Signifies the slower value of the positive or negative slew rate.
(4) Third-order filter; bandwidth = 80 kHz at –3 dB.

6.8 Typical Characteristics

Table 1. Characteristic Performance Measurements

TITLE FIGURE
Open-Loop Gain and Phase vs Frequency Figure 1
Open-Loop Gain vs Temperature Figure 2
Quiescent Current vs Supply Voltage Figure 3
Quiescent Current vs Temperature Figure 4
Offset Voltage Production Distribution Figure 5
Offset Voltage Drift Distribution Figure 6
Offset Voltage vs Common-Mode Voltage (Maximum Supply) Figure 7
Offset Voltage vs Temperature Figure 8
CMRR and PSRR vs Frequency (RTI) Figure 9
CMRR and PSRR vs Temperature Figure 10
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V) Figure 11
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V) Figure 12
Input Voltage Noise vs Common-Mode Voltage (5.5 V) Figure 13
Input Bias and Offset Current vs Temperature Figure 14
Open-Loop Output Impedance vs Frequency Figure 15
Maximum Output Voltage vs Frequency and Supply Voltage Figure 16
Output Voltage Swing vs Output Current (over Temperature) Figure 17
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V) Figure 18
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (5.5 V) Figure 19
Small-Signal Overshoot vs Load Capacitance Figure 20
Small-Signal Step Response, Noninverting (1.8 V) Figure 21
Small-Signal Step Response, Noninverting ( 5.5 V) Figure 22
Large-Signal Step Response, Noninverting (1.8 V) Figure 23
Large-Signal Step Response, Noninverting ( 5.5 V) Figure 24
Positive Overload Recovery Figure 25
Negative Overload Recovery Figure 26
No Phase Reversal Figure 27
Channel Separation vs Frequency (Dual) Figure 28
THD+N vs Amplitude (G = 1, 2 kΩ, 10 kΩ) Figure 29
THD+N vs Amplitude (G = –1, 2 kΩ, 10 kΩ) Figure 30
THD+N vs Frequency (0.5 VRMS, G = +1, 2 kΩ, 10 kΩ) Figure 31
EMIRR Figure 32
At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
OPA314 OPA2314 OPA4314 tc_open_loop_gain_phase_fqcy_bos563.gif
Figure 1. Open-Loop Gain and Phase vs Frequency
OPA314 OPA2314 OPA4314 tc_iq_vsupply_bos563.gif
Figure 3. Quiescent Current vs Supply
OPA314 OPA2314 OPA4314 tc_histo_voffset_bos563.gif
Figure 5. Offset Voltage Production Distribution
OPA314 OPA2314 OPA4314 tc_vos_vcm_bos563.gif
Figure 7. Offset Voltage vs Common-Mode Voltage
OPA314 OPA2314 OPA4314 tc_cmrr_psrr_fqcy_bos563.gif
Figure 9. CMRR and PSRR vs Frequency (Referred-to-Input)
OPA314 OPA2314 OPA4314 tc_input_volt_noise_bos563.gif
Figure 11. 0.1-Hz to 10-Hz Input Voltage Noise
OPA314 OPA2314 OPA4314 tc_vnoise_vcm_bos563.gif
Figure 13. Voltage Noise vs Common-Mode Voltage
OPA314 OPA2314 OPA4314 tc_open_loop_output_imped_fqcy_bos563.gif
Figure 15. Open-Loop Output Impedance vs Frequency
OPA314 OPA2314 OPA4314 tc_vout_swing_iout_bos563.gif
Figure 17. Output Voltage Swing vs Output Current (Over Temperature)
OPA314 OPA2314 OPA4314 tc_closed_loop_gain_fqcy_55v_bos563.gif
Figure 19. Closed-Loop Gain vs Frequency
OPA314 OPA2314 OPA4314 tc_sm_sig_step_09V_bos563.gif
Figure 21. Small-Signal Pulse Response (Noninverting)
OPA314 OPA2314 OPA4314 tc_lg_sig_step_09V_bos563.gif
Figure 23. Large-Signal Pulse Response (Noninverting)
OPA314 OPA2314 OPA4314 tc_ovrload_recover_pos_bos563.gif
Figure 25. Positive Overload Recovery
OPA314 OPA2314 OPA4314 tc_anti_phase_reversal_bos563.gif
Figure 27. No Phase Reversal
OPA314 OPA2314 OPA4314 tc_thdn_out_ampl_g1_bos563.gif
Figure 29. THD+N vs Output Amplitude (G = 1 V/V)
OPA314 OPA2314 OPA4314 tc_thdn_fqcy_g1_bos563.gif
Figure 31. THD+N vs Frequency
OPA314 OPA2314 OPA4314 tc_open_loop_gain_temp_bos563.gif
Figure 2. Open-Loop Gain vs Temperature
OPA314 OPA2314 OPA4314 tc_iq_temp_bos563.gif
Figure 4. Quiescent Current vs Temperature
OPA314 OPA2314 OPA4314 tc_histo_voffset_drift_bos563.gif
Figure 6. Offset Voltage Drift Distribution
OPA314 OPA2314 OPA4314 tc_vos_temp_bos563.gif
Figure 8. Offset Voltage vs Temperature
OPA314 OPA2314 OPA4314 tc_cmrr_psrr_temp_bos563.gif
Figure 10. CMRR and PSRR vs Temperature
OPA314 OPA2314 OPA4314 tc_vin_spec_density_fqcy_bos563.gif
Figure 12. Input Voltage Noise Spectral Density vs Frequency
OPA314 OPA2314 OPA4314 tc_input_bias_temp_bos563.gif
Figure 14. Input Bias and Offset Current vs Temperature
OPA314 OPA2314 OPA4314 tc_max_vout_fqcy_bos563.gif
Figure 16. Maximum Output Voltage vs Frequency and Supply Voltage
OPA314 OPA2314 OPA4314 tc_closed_loop_gain_fqcy_18v_bos563.gif
Figure 18. Closed-Loop Gain vs Frequency
OPA314 OPA2314 OPA4314 tc_sm_sig_ovrsht_cap_load_bos563.gif
Figure 20. Small-Signal Overshoot vs Load Capacitance
OPA314 OPA2314 OPA4314 tc_sm_sig_step_275V_bos563.gif
Figure 22. Small-Signal Pulse Response (Inverting)
OPA314 OPA2314 OPA4314 tc_lg_sig_step_275V_bos563.gif
Figure 24. Large-Signal Pulse Response (Inverting)
OPA314 OPA2314 OPA4314 tc_ovrload_recover_neg_bos563.gif
Figure 26. Negative Overload Recovery
OPA314 OPA2314 OPA4314 tc_chan_separat_fqcy_bos563.gif
Figure 28. Channel Separation vs Frequency OPA2314
OPA314 OPA2314 OPA4314 tc_thdn_out_ampl_g-1_bos563.gif
Figure 30. THD+N vs Output Amplitude (G = –1 V/V)
OPA314 OPA2314 OPA4314 tc_emirr_2314_bos563.png
Figure 32. Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR IN+) vs Frequency