at TA =
25°C, VS = ±2.75 V, RL = 10 kΩ connected to VS / 2,
VCM = VS / 2, and VOUT = VS / 2, unless
otherwise noted.
Figure 7-39 Offset Voltage
Production Distribution
Figure 7-41 Offset Voltage
vs Temperature (PMOS Input Pair)
| Over full common-mode
voltage range |
Figure 7-43 Offset Voltage
vs Common-Mode Voltage (Full Range)
Figure 7-45 Offset Voltage
vs Common-Mode Voltage (Transition Region)
Figure 7-47 IB
and IOS vs Common-Mode Voltage
Figure 7-49 0.1-Hz to 10-Hz
Flicker Noise
Figure 7-51 CMRR and PSRR
vs Frequency (Referred to Input)
Figure 7-53 PSRR vs
Temperature
Figure 7-55 Closed-Loop
Gain vs Frequency
Figure 7-57 Open-Loop Gain
vs Output Voltage
Figure 7-59 No Phase
Reversal
| VCM =
VS / 2, RL = 1 kΩ |
| Gain = +1, 100-mV output
step |
Figure 7-61 Small-Signal
Overshoot vs Load Capacitance
| CL = 20
pF, Gain = 1, VIN = 100-mVpp, RL = 1 kΩ |
Figure 7-63 Small-Signal
Step Response
| CL = 20 pF,
Gain = +1, VIN = 2-V step, RL = 1 kΩ |
Figure 7-65 Large Signal
Step Response
| CL = 20 pF,
Gain = 1, VIN = 2-V step |
Figure 7-67 Large Signal
Settling Time (Positive)
| VCM = 2.5
V |
| Gain = +1, BW = 80 kHz,
VOUT = 0.5 Vrms |
Figure 7-69 THD + N vs
Frequency
Figure 7-71 VOUT
vs Sourcing Current
| CL = 10 pF,
Gain = +1, VS= 5.5 V |
Figure 7-73 Maximum Output
Voltage vs Frequency
Figure 7-75 Quiescent
Current vs Supply Voltage
Figure 7-77 Open-Loop
Output Impedance vs Frequency
Figure 7-79 Electromagnetic
Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs
Frequency
Figure 7-40 Offset Voltage
Drift Distribution
Figure 7-42 Offset Voltage
vs Temperature (NMOS Input Pair)
Figure 7-44 Offset Voltage
vs Common-Mode Voltage (PMOS Input Pair)
Figure 7-46 Offset Voltage
vs Power Supply
Figure 7-48 IB
and IOS vs Temperature
Figure 7-50 Input Voltage
Noise Spectral Density vs Frequency
| VS = 5.5 V,
VCM = V– to (V+) – 1.2 V |
Figure 7-52 CMRR vs
Temperature
Figure 7-54 Open-Loop Gain
and Phase vs Frequency
Figure 7-56 Open-Loop Gain
vs Temperature
Figure 7-58 Phase Margin vs
Capacitive Load
| VCM =
VS / 2, RL = 1 kΩ |
| Gain = –1, 100-mV output
step |
Figure 7-60 Small-Signal
Overshoot vs Load Capacitance
| VIN = 0.6
Vpp, G = –10, VIN × gain > VS |
|
|
|
Figure 7-62 Overload
Recovery
| CL = 20
pF, Gain = –1, VIN = 100-mVpp, RL = 1 kΩ |
Figure 7-64 Small-Signal
Step Response
| CL = 20 pF,
Gain = –1, VIN = 2-V step, RL = 1 kΩ |
Figure 7-66 Large Signal
Step Response
| CL = 20 pF,
Gain = –1, VIN = 2-V step |
Figure 7-68 Large Signal
Settling Time (Negative)
Figure 7-70 THD + N vs
Amplitude
Figure 7-72 VOUT
vs Sinking Current
Figure 7-74 Short-Circuit
Current vs Temperature
Figure 7-76 Quiescent
Current vs Temperature
| AVDD = 5.5 V,
VICM = VOCM = 2.75 V |
Figure 7-78 Channel
Separation vs Frequency
| VS = 0 to 5.5
V, VOUT = 0 to 2.75 V |
Figure 7-80 Turn-On
Time