The aim of this application section is to measure bidirectional current with relatively high accuracy in a low-side-sensing-based, high-frequency switching system.

As shown in Figure 9-12, a single op amp of high bandwidth is capable of sensing current in a high gain configuration as well as have the required effective bandwidth to drive the consecutive SAR ADC input. The SAR ADC can be a standalone ADC or integrated inside a Micro-controller.

The reference voltage is 1.24 V. When the I_SH flowing across R_SH equals zero, the V_OUT of the difference amplifier sits ideal at 1.24 V.

When the current (I_SH) flows from LOAD to GND, the output of the OPAx607-Q1 increase above 1.24 V with a value equal to 20 × V_SH and when the current flows from GND to LOAD (in the opposite direction) the output of the OPAx607-Q1 decrease below 1.24 V with a value proportional to 20 × V_SH.

One of the main challenges in a high speed current sensing design is to choose an op amp of with sufficient GBW that can drive a SAR ADC, while still being able to gain the signal by the required amount. The 0.1% and 0.01% settling of OPAx607-Q1 can found in Section 7.5. Another key care about is to ensure the op amp output rises in less than 1 µs so as to feed the output to a comparator for short-circuit protection. This comparator based short circuit protection loop is extremely fast and enables to turn off the switching devices very quickly. This requirement makes a low cost high speed part like the OPAx607-Q1 very desirable in a current-sensing circuit. Equation of the rise time as a function of bandwidth is shown below.

For an ADC like ADS7042 running at a sampling rate of 500 kSPS of a clock of 12.5 MHz, the effective bandwidth of the op amp required to drive such an ADC is approximately 2.7 MHz. See the TI precision lab videos on driving SAR ADCs to understand the underlying calculation. The OPAx607-Q1 has a GBW of 50 MHz. With a gain of 20 V/V, the closed loop bandwidth turns out to approximately 2.5 MHz, making this device the most suitable, cost-optimized amplifier for this application. The RC charge bucket (240 Ω and 688 pF in Figure 9-12) designed at the input of the SAR ADC is derived from the calculations provided in the SAR ADC precision lab videos. The fundamental concept behind the design of this charge bucket filter is to ensure that the sample and hold capacitor is charged to the required final voltage within the acquisition window of the ADC.

As shown in Figure 9-14, a DC accuracy of higher than 0.05% is achieved with the OPAx607-Q1. The simulations are captured with and without voltage offset calibration. Frequency response shown in Figure 9-13 indicate different signal bandwidth at V_OUT, V_ADC and with and without C_F of 220 pF.