9.2.1.1 Design Requirements

SAR ADCs, such as the ADS8860, use sampling capacitors on the data converter input. During the signal acquisition phase, these sampling capacitors are connected to the ADC analog input terminals, AINP and AINN, through a set of switches. After the acquisition period has elapsed, the internal sampling capacitors are disconnected from the input terminals and connected to the input of the ADC through a second set of switches, during this period the ADC is performing the analog-to-digital conversion. Figure 74 illustrates this architecture.

Figure 74. Simplified SAR ADC Input

The SAR ADC inputs and sampling capacitors must be driven by the OPA625 to 16-bit levels within the acquisition time of the ADC. For the example illustrated in Figure 73, the OPA625 is used to drive the ADS8860 at a sample rate of 1 MSPS.

9.2.1.2 Detailed Design Procedure

The circuit illustrated in Figure 73 consists of the SAR ADC driver, a low-pass filter and the SAR ADC. The SAR ADC driver circuit consists of an OPA625 configured in an inverting gain of 1. The filter consists of R_FLT and C_FLT, connected between the output of the OPA625 and input of the ADS8860. Selecting the proper values for each of these passive components is critical to obtain the best performance from the ADC. Capacitor C_FLT serves as a charge reservoir, providing the necessary charge to the ADC sampling capacitors. The dynamic load presented by the ADC creates a glitch on the filter capacitor, C_FLT. To minimize the magnitude of this glitch, choose a value for C_FLT large enough to maintain a glitch amplitude of less than 100 mV. Maintaining such a low glitch amplitude at the amplifier output makes sure that the amplifier remains in the linear operating region, and results in a minimum settling time. Using Equation 6, a 10-nF capacitor is selected for C_FLT.

Equation 6.

Connecting a 10-nF capacitor directly to the output of the OPA625 degrades the OPA625 phase margin and results in stability and settling-time problems. To properly drive the 10-nF capacitor, use a series resistor (R_FLT) to isolate the capacitor, C_FLT, from the OPA625. R_FLT must be sized based upon several constraints. To determination a suitable value for R_FLT, consider the impact upon the THD due to the voltage divider effect from R_FLT reacting with the switch resistance (R_SW) of the ADC input circuit, as well as the impact of the output impedance upon amplifier stability. In this example, 4.7-Ω resistors are selected. In this design example, Figure 16 can be used to estimate a suitable value for R_ISO. R_ISO represents the total resistance in series with C_FLT, and in this example is equivalent to 2 × R_FLT.

	For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results, refer to TI Precision Design, TIDU014, "Power-optimized 16-bit 1MSPS Data Acquisition Block for Lowest Distortion and Noise Reference Design".

9.2.1.3 Application Curves

Figure 75 illustrates the performance of the circuit shown in Figure 73.

4096-point FFT at 1 MSPS, fIN = 10 kHz , VIN = 1.5 VRMS

Figure 75. ADC Output FFT for Figure 73

9.2.2.1 Design Requirements

To optimize this circuit for performance, this design does not allow any large signal input transients at the inputs of the driver circuit for a small quiet-time period (t_QT) towards the end of the previous conversion. The input step voltage can appear anytime from the beginning of conversion (CONVST rising edge) until the elapse of a half cycle time (0.5 × t_CYC). This timing constraint on the input step allows a minimum settling time of (t_QT + t_ACQ) for the ADC input to settle within the required accuracy, in the worst-case scenario. This provides more time for the amplifier's output to slew and settle within the required accuracy before the next conversion starts. Figure 77 illustrates this timing sequence.

Figure 77. Timing Diagram for Input Signals

9.2.2.2 Detailed Design Procedure

An ADC input driver circuit mainly consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides a buffer between the signal source and the ADC input. The RC filter helps attenuate the sampling charge-injection from the switched-capacitor input stage of the ADC as well as acts as an anti-aliasing filter to band-limit the wideband noise contributed by the front-end circuit. The design of the ADC input driver involves optimizing the bandwidth of the circuit, driven primarily by the following requirements:

• The R_FLTC_FLT filter bandwidth should be low to band-limit the noise fed into the input of the ADC thereby increasing the signal-to-noise ratio (SNR) of the system.
• The overall system bandwidth should be large enough to accommodate optimal settling of the input signal at the ADC input before the start of conversion.

C_FLT is chosen based upon Equation 7 . C_FLT is chosen to be 1 nF.

Equation 7.

Connecting a 1-nF capacitor directly to the output of the OPA625 would degrade the OPA625 phase margin and result in stability and settling time problems. To properly drive the 1-nF capacitor, a series resistor, R_FLT, is used to isolate the capacitor, C_FLT, from the OPA625. R_FLT must be sized based upon several constraints. To determination a suitable value for R_FLT, the system designer must consider the impact upon the THD due to the voltage divider effect from R_FLT reacting with the switch resistance, R_SW, of the ADC input circuit as well as the impact of the output impedance upon amplifier stability. In this example 12.4-Ω resistors are selected. In this design example, Figure 15 can be used to estimate a suitable value for R_ISO. R_ISO represents the total resistance in series with C_FLT, which in this example is equivalent to 2 × R_FLT.

	For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results, refer to TI Precision Design, TIDU012, "Power-optimized 16-bit 1MSPS Data Acquisition Block for Lowest Distortion and Noise Reference Design".

9.2.2.3 Application Curves

Figure 78 illustrates the performance of the circuit shown in Figure 76.

I.

Figure 78. Positive Transient Response for Figure 76

i.

Figure 79. Negative Transient Response for Figure 76