JAJSFO4B August   2017  – December 2018 OPA2810

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     マルチチャネル・センサ・インターフェイス
  3. 3 概要
    1.     高調波歪みと周波数との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: 10 V
    6. 6.6  Electrical Characteristics: 24 V
    7. 6.7  Electrical Characteristics: 5 V
    8. 6.8  Typical Characteristics: VS = 10 V
    9. 6.9  Typical Characteristics: VS = 24 V
    10. 6.10 Typical Characteristics: VS = 5 V
    11. 6.11 Typical Characteristics: ±2.375 V to ±12 V Split Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 ESD Protection
    3. 7.3 Feature Description
      1. 7.3.1 OPA2810 Comparison
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±2.375 V to ±13.5 V)
      2. 7.4.2 Single-Supply Operation (4.75 V to 27 V)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Selection of Feedback Resistors
      2. 8.1.2 Noise Analysis and the Effect of Resistor Elements on Total Noise
    2. 8.2 Typical Applications
      1. 8.2.1 Transimpedance Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Multichannel Sensor Interface
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Thermal Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics: 24 V

Test conditions unless otherwise noted: TA = 25°C, VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to midsupply(5).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Test Level(3)
AC PERFORMANCE
SSBW Small-signal bandwidth G = 1, Vo = 20 mVPP, RF = 0 Ω 75 MHz C
G = 1, Vo = 20 mVPP, RF = 0 Ω,
CL= 33 pF		 105 MHz C
G = –1, Vo = 20 mVPP 51 MHz C
G = 2, Vo = 20 mVPP 49 MHz C
G = 5, Vo = 20 mVPP 15 MHz C
LSBW Large-signal bandwidth G = 2 Vo = 2 VPP 38 MHz C
G = 2 Vo = 10 VPP 14 MHz C
GBWP Gain-bandwidth product G = 11, Vo = 20 mVPP 70 MHz C
Bandwdith for 0.1dB flatness G = 2, Vo = 20 mVPP 12 MHz C
SR Slew rate (20%-80%)(4) G = 2, Vo = –2-V to 2-V step 226 V/µs C
G = –1, Vo = –2-V to 2-V step 218 V/µs C
G = 2, Vo = –4.5-V to 3.5-V step 243 V/µs C
Rise time Vo = 200-mV step 4 ns C
Fall time Vo = 200-mV step 5 ns C
Settling time to 0.1% G = 2, Vo = 2-V step 72 ns C
G = 2, Vo = 10-V step 90 ns C
G = –1, Vo = 10-V step 89 ns C
Settling time to 0.001% G = 2, Vo = 2-V step 370 ns C
G = 2, Vo = 10-V step 210 ns C
G = –1, Vo = 10-V step 150 ns C
Overshoot/undershoot G = 1, RF = 0 Ω, Vo = 200 mVPP 7.5/9 % C
G = 1, RF = 0 Ω, Vo = 2 VPP 4/5 % C
Input overdrive recovery G = 1, RF = 0 Ω, (VS– – 0.5 V) to
(VS+ + 0.5 V) input (see Figure 31)		 66 ns C
Output overdrive recovery G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V) input (see Figure 32) 30 ns C
HD2 Second-order harmonic distortion f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP –123 dBc C
f = 100 kHz, RL =1 kΩ, Vo = 10 VPP –113 dBc C
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP –105 dBc C
f = 1 MHz, RL=1 kΩ, Vo = 10 VPP –92 dBc C
HD3 Third-order harmonic distortion f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP –134 dBc C
f = 100 kHz, RL =1 kΩ, Vo = 10 VPP –130 dBc C
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP –103 dBc C
f = 1 MHz, RL =1 kΩ, Vo = 10 VPP –86 dBc C
en Input-referred voltage noise f = 500 kHz, flatband 6 nV/√Hz C
f = 0.1-10 Hz integrated 0.36 µVrms C
ei Input-referred current noise f = 10 kHz 5 fA/√Hz C
zO Close-loop output impedance f = 100 kHz 0.007 Ω C
DC PERFORMANCE
AOL Open-loop voltage gain f = DC, Vo = ±8 V 108 120 dB A
TA = –40°C to +125°C 108 dB B
VOS Input offset voltage TA = 25°C 0.1 1.5 mV A
TA = –40°C to +85°C 2.4 mV B
TA = –40°C to +125°C 2.8 mV B
Input offset voltage drift TA = 25°C 1.5 µV/°C B
TA = –40°C to +125°C 13 µV/°C B
Input bias current TA = 25°C 2 20 pA A
TA = –40°C to +85°C(6) 20 60 pA B
TA = –40°C to +125°C(6) 100 460 pA B
Input offset current TA = 25°C 1 20 pA A
TA = –40°C to +85°C 5 pA B
TA = –40°C to +125°C 50 pA B
CMRR Common-mode rejection ratio f = DC, TA = 25°C, VCM = ±5 V 90 105 dB A
TA = –40°C to +125°C 90 dB B
INPUT
Allowable input differential voltage see Figure 57 ±7 V C
Common-mode input impedance In closed-loop configuration 12 || 2.5 GΩ||pF C
Differential input capacitance In open-loop configuration 0.5 pF C
Most positive input voltage ΔVOS < 5 mV(1) VS+ + 0.2 VS+ + 0.3 V A
TA = –40°C to +125°C VS+ + 0.1 V B
Most negative input voltage ΔVOS < 5 mV(1) VS– – 0.2 VS– – 0.3 V A
TA = –40°C to +125°C VS– – 0.2 V B
Most positive input voltage for main-JFET stage TA = 25°C (see Figure 35) VS+ – 2.9 VS+ – 2.5 V C
TA = –40°C to +125°C VS+ – 3 V C
OUTPUT
VOCRH Output voltage range high TA = 25°C, RL = 667 Ω VS+ – 0.33 VS+ – 0.22 V A
TA = –40°C to +125°C, RL = 667 Ω VS+ – 0.36 V B
VOCRL Output voltage range low TA = 25°C, RL = 667 Ω VS– + 0.23 VS– + 0.15 V A
TA = –40°C to +125°C, RL = 667 Ω VS– + 0.33 V B
IO(max) Linear output drive (sourcing and sinking) TA = 25°C, Vo = 7.25 V, RL = 151 Ω, VOS < 2 mV 48 64 mA A
TA = –40°C to +90°C, Vo = 4.35 V, VOS < 2 mV 29 mA B
ISC Output short-circuit current TA = 25°C, TDelay = 5 ms 108 mA B
CL Capacitive load drive < 1 dB peaking, RS = 0 Ω 35 pF C
POWER SUPPLY
VS Operating voltage TA = 25°C 4.75 27 V A
TA = –40°C to +125°C 4.75 27 V B
IQ Quiescent current per channel TA = 25°C 3.2 3.7 4.1 mA A
TA = –40°C to +125°C 3.0 4.5 mA B
PSRR Power supply rejection ratio ΔVS = 2 V(2) 90 105 dB A
TA = –40°C to +125°C 90 dB B
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product VCM = VS+ – 1 V 35 MHz C
Open-loop voltage gain VCM = VS+ – 1 V, f = DC, Vo = 7 V to –7 V 80 95 dB A
Input-referred voltage noise VCM = VS+ – 1 V, f = 1 MHz 21 nV/√Hz C
Input offset voltage VCM = VS+ – 1.5 V, no-load 4 mV A
VCM = VS+ – 0.5 V, no-load 4.8 mV A
VCM = VS+ – 0.5 V, TA = –40°C to +125°C, no-load 6.4 mV B
Input bias current VCM = VS+ – 1.5 V 2 24 pA A
VCM = VS+ – 1.5 V, TA = –40°C to +125°C 0.15 1 nA B
Common-mode rejection ratio VCM = VS+ – 1.5 V to VS+ – 0.5 V 75 dB B
Power supply rejection ratio VCM = VS+ – 1.5 V, ΔVS = ±2 V(2) 70 dB B
CHANNEL MATCHING
Channel-to-channel GBWP mismatch TA = 25°C 3 % C
Channel-to-channel crosstalk f = 100 kHz -93 dBc C
Input offset voltage mismatch TA = 25°C 0.1 2.5 mV A
(1) Change in input offset from its value when input is biased to midsupply.
(2) The supply voltages are VS+ = 12 V ± 1 V and VS– = –12 V for +PSRR, and VS+ = 12 V and VS– = –12 V ± 1 V for –PSRR.
(3) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(4) Lower of the measured positive and negative slew rate.
(5) For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted).
(6) Maximum bias current specification is set using ±5σ limits (corresponding to 0.58 DPPM) obtained using the statistical distribution from electrical characterization over temperature of a sample set of 70 units. Maximum specification is not specified by final automated test equipment (ATE) nor by QA sample testing.