JAJSFO4B August   2017  – December 2018 OPA2810

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     マルチチャネル・センサ・インターフェイス
  3. 3 概要
    1.     高調波歪みと周波数との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: 10 V
    6. 6.6  Electrical Characteristics: 24 V
    7. 6.7  Electrical Characteristics: 5 V
    8. 6.8  Typical Characteristics: VS = 10 V
    9. 6.9  Typical Characteristics: VS = 24 V
    10. 6.10 Typical Characteristics: VS = 5 V
    11. 6.11 Typical Characteristics: ±2.375 V to ±12 V Split Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 ESD Protection
    3. 7.3 Feature Description
      1. 7.3.1 OPA2810 Comparison
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±2.375 V to ±13.5 V)
      2. 7.4.2 Single-Supply Operation (4.75 V to 27 V)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Selection of Feedback Resistors
      2. 8.1.2 Noise Analysis and the Effect of Resistor Elements on Total Noise
    2. 8.2 Typical Applications
      1. 8.2.1 Transimpedance Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Multichannel Sensor Interface
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Thermal Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2 Functional Block Diagram

The OPA2810 features a true high-impedance input stage including a JFET differential-input pair main stage and a CMOS differential-input auxiliary (Aux) stage operational within 2.5 V of the positive supply voltage. The bias current is limited to a maximum of 20 pA throughout the common-mode input range of the amplifier. Figure 62 shows a block diagram representation for the input stage of the OPA2810.

OPA2810 Input-BD-SBOS789.gifFigure 62. Input-Stage Block Diagram

The amplifier exhibits superior performance for high-speed signals (distortion, noise and input offset voltage) while the Aux stage enables rail-to-rail inputs and prevents phase reversal. The OPA2810 also includes input clamps which enable maximum input differential voltage of upto 7 V (lower of 7 V and total supply voltage). This architecture offers significantly greater differential input voltage capability as compared to one to two times the diode forward voltage drop maximum rating in standard amplifiers, and makes this device suitable for use with multiplexers and processing of signals with fast transients. The input bias currents are also clamped to maximum 300 µA, as Figure 57 shows, which does not load the previous driver stage or require current-limiting resistors (except limiting current through the input ESD diodes when input common-mode voltages are greater than the supply voltages). This also enables the use of one of the channels as a comparator in systems which require an amplifier and a comparator for signal-gain and fault-detection, respectively. For the lowest offset, distortion and noise performance, limit the common-mode input voltage to the main JFET-input stage (greater than 2.5 V away from the positive supply).

The OPA2810 is a rail-to-rail output amplifier and swings to either of the rails at the output, as shown in Figure 16 for 10-V supply operation. This is particularly useful for inputs biased near the rails or when the amplifier is configured in a closed-loop gain such that the output approaches the supply voltage. When the output saturates, it recovers with 55 ns when inputs exceed the supply voltages by 0.5 V in an G = –1 V/V inverting gain with a 10–V supply. The outputs are short-circuit protected with the limits of Figure 17.

An amplifier phase margin reduces and it becomes unstable when driving a capacitive load (CL) at the output, as Figure 63 shows. Use of a series resistor (RS) between the amplifier output and load capacitance introduces a zero which cancels the pole formed by the amplifier output impedance and CL in the open-loop transfer function. The OPA2810 drives capacitive loads of up to 35 pF without causing instability. It is recommended to use a series resistor for larger load capacitance values, as Figure 4 shows for OPA2810 configured as a unity-gain buffer.

OPA2810 Driving_Capacitive_Loads.gifFigure 63. OPA2810 Driving Capacitive Load