SBOS309E August   2004  – December 2024 OPA2830

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configurations and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics VS = ±5V
    6. 6.6  Electrical Characteristics VS = 5V
    7. 6.7  Electrical Characteristics VS = 3V
    8. 6.8  Typical Characteristics: VS = ±5V
    9. 6.9  Typical Characteristics: VS = ±5V, Differential Configuration
    10. 6.10 Typical Characteristics: VS = 5V
    11. 6.11 Typical Characteristics: VS = 5V, Differential Configuration
    12. 6.12 Typical Characteristics: VS = 3V
    13. 6.13 Typical Characteristics: VS = 3V, Differential Configuration
  8. Parameter Measurement Information
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Wideband Voltage-Feedback Operation
      2. 8.1.2  Single-Supply ADC Interface
      3. 8.1.3  DC Level-Shifting
      4. 8.1.4  AC-Coupled Output Video Line Driver
      5. 8.1.5  Noninverting Amplifier With Reduced Peaking
      6. 8.1.6  Single-Supply Active Filter
      7. 8.1.7  Differential Low-Pass Active Filters
      8. 8.1.8  High-Pass Filters
      9. 8.1.9  High-Performance DAC Transimpedance Amplifier
      10. 8.1.10 Operating Suggestions Optimizing Resistor Values
      11. 8.1.11 Bandwidth vs Gain: Noninverting Operation
      12. 8.1.12 Inverting Amplifier Operation
      13. 8.1.13 Output Current and Voltages
      14. 8.1.14 Driving Capacitive Loads
      15. 8.1.15 Distortion Performance
      16. 8.1.16 Noise Performance
      17. 8.1.17 DC Accuracy and Offset Control
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 Thermal Analysis
    3. 8.3 Layout
      1. 8.3.1 Board Layout Guidelines
        1. 8.3.1.1 Input and ESD Protection
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Design-In Tools
        1. 9.1.1.1 Demonstration Fixtures
        2. 9.1.1.2 Macro-model and Applications Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • D|8
  • DGK|8
サーマルパッド・メカニカル・データ
発注情報

DC Accuracy and Offset Control

The balanced input stage of a wide-band voltage-feedback op amp allows good output dc accuracy in a wide variety of applications. The power-supply current trim for the OPA2830 gives even tighter control than comparable products. Although the high-speed input stage does require relatively high input bias current (typically 5μA out of each input terminal), the close matching between them can be used to reduce the output dc error caused by this current. This is done by matching the dc source resistances appearing at the two inputs. Evaluating the configuration of Figure 8-3 (which has matched dc input resistances), using worst-case +25°C input offset voltage and current specifications, gives a worst-case output offset voltage equal to:

  • (NG = noninverting signal gain at dc)
  • ±(NG × VOS(MAX)) + (RF × IOS(MAX))
  • = ±(2 × 7.5mV) × (375Ω × 1.1μA)
  • = ±15.41mV

A fine-scale output offset null, or dc operating point adjustment, is often required. Numerous techniques are available for introducing dc offset control into an op amp circuit. Most of these techniques are based on adding a dc current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the noninverting input can be considered. Bring the dc offsetting current into the inverting input node through resistor values that are much larger than the signal path resistors. This insure that the adjustment circuit has minimal effect on the loop gain and hence the frequency response.