JAJSDR3D September   2017  – December 2018 OPA2837 , OPA837

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     真のグランド入力および出力範囲を備えた低消費電力、低ノイズ、高精度、シングルエンドSAR ADCドライバ
  3. 3 概要
    1.     Device Images
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information: OPA837
    5. 6.5  Thermal Information: OPA2837
    6. 6.6  Electrical Characteristics: VS = 5 V
    7. 6.7  Electrical Characteristics: VS = 3 V
    8. 6.8  Typical Characteristics: VS = 5.0 V
    9. 6.9  Typical Characteristics: VS = 3.0 V
    10. 6.10 Typical Characteristics: ±2.5-V to ±1.5-V Split Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 OPA837 Comparison
      2. 7.3.2 Input Common-Mode Voltage Range
      3. 7.3.3 Output Voltage Range
      4. 7.3.4 Power-Down Operation
      5. 7.3.5 Low-Power Applications and the Effects of Resistor Values on Bandwidth
      6. 7.3.6 Driving Capacitive Loads
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 7.4.2 Single-Supply Operation (2.7 V to 5.4 V)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Noninverting Amplifier
      2. 8.1.2  Inverting Amplifier
      3. 8.1.3  Output DC Error Calculations
      4. 8.1.4  Output Noise Calculations
      5. 8.1.5  Instrumentation Amplifier
      6. 8.1.6  Attenuators
      7. 8.1.7  Differential to Single-Ended Amplifier
      8. 8.1.8  Differential-to-Differential Amplifier
      9. 8.1.9  Pulse Application With Single-Supply Circuit
      10. 8.1.10 ADC Driver Performance
    2. 8.2 Typical Applications
      1. 8.2.1 Active Filters
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Implementing a 2:1 Active Multiplexer
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 1-Bit PGA Operation
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.2 Inverting Amplifier

The OPAx837 can be used as an inverting amplifier with a signal input to the inverting input, VIN–, through the gain-setting resistor RG. A basic block diagram of the circuit is illustrated in Figure 63.

The output of the amplifier can be calculated according to Equation 3 if VIN = VREF + VSIG and the noninverting input is biased to VREF.

Equation 3. OPA837 OPA2837 EQ2_vout2_los713.gif

The signal gain of the circuit is set by Equation 4 and VREF provides a reference point around which the input and output signals swing. For bipolar-supply operation, VREF is often ground. The output signal is 180˚ out-of-phase with the input signal in the pass band of the application. Figure 75 shows the 50-Ω input matched configuration used for the inverting characterization plots set up for a gain of –1 V/V. In this case, an added termination resistor, RT, is placed in parallel with the input RG resistor to provide an impedance match to 50-Ω test equipment. The output network appears as a 2-kΩ load but with a 50-Ω source to the network analyzer. This output interface network does add a 37.9-dB insertion loss that is normalized out in the characterization curves. Table 3 lists the suggested values for RF, RG, and RT for inverting gains from –0.5 V/V to –10 V/V. If a 50-Ω input match is not required, eliminate the RT element.

Equation 4. OPA837 OPA2837 Iline2_G2_los713.gif
OPA837 OPA2837 sbos673_sch_Inverting_GainX1.gifFigure 75. Inverting Characterization Circuit for Network Analyzer

Table 3. Inverting Recommended Resistor Values

INVERTING GAIN (V/V) RF (Ω) RG (Ω) STANDARD RT (Ω) INPUT ZI (Ω) ACTUAL (V/V) GAIN (dB)
–0.5 1190 2370 51.1 50.02 –0.50 –5.98
–1 2000 2000 51.1 49.83 –1.00 0.00
–2 2260 1130 52.3 49.99 –2.00 6.02
–3 2370 787 53.6 50.18 –3.01 9.58
–4 2490 619 54.9 50.43 –4.02 12.09
–5 2550 511 54.9 49.57 –4.99 13.96
–6 2610 432 56.2 49.73 –6.04 15.62
–7 2670 383 57.6 50.07 –6.97 16.87
–8 2670 332 59 50.10 –8.04 18.11
–9 2670 294 60.4 50.11 –9.08 19.16
–10 2670 267 61.9 50.25 –10.00 20.00