JAJSO90A february 2023 – july 2023 OPA2863-Q1
PRODUCTION DATA
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In a difference amplifier circuit, the output voltage is given by:
For lowest system noise, small values of RF and RG are preferred. The smallest value of RG is limited by the input transient voltage (10 V here) seen by the circuit, and is given by:
where
For a difference amplifier gain of 20 V/V, an RF of 12 kΩ and RG of 600 Ω are used. With a clock frequency of 40 MHz and ADS7056 sampling at 1 MSPS, the available acquisition time for amplifier output settling is 550 ns. Table 9-1 shows the simulation results for the circuit in Figure 9-1. The worst-case peak-to-peak input transient condition is simulated. The output of the OPA2863-Q1 settles to within 0.1% accuracy within 543 ns. If using a slower clock frequency with the ADC is desired, then the acquisition time reduces with the same sampling rate, which degrades measurement accuracy. Alternatively, the sampling rate can be reduced to recover the required acquisition time and 0.1% accuracy.