JAJSS74 November   2023 OPA2994-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Unlimited Capacitive Load Drive
      2. 6.3.2 EMI Rejection
      3. 6.3.3 Common-Mode Voltage Range
      4. 6.3.4 Phase Reversal Protection
      5. 6.3.5 Electrical Overstress
      6. 6.3.6 Overload Recovery
      7. 6.3.7 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

5.5 Thermal Information for Dual Channel

THERMAL METRIC(1)OPA2994-Q1Unit
D
(SOIC)		DGK
(VSSOP)
8 PINS8 PINS
RθJAJunction-to-ambient thermal resistanceTBDTBD  °C/W
RθJC(top)Junction-to-case (top) thermal resistanceTBDTBD  °C/W
RθJBJunction-to-board thermal resistanceTBDTBD  °C/W
ψJTJunction-to-top characterization parameterTBDTBD  °C/W
ψJBJunction-to-board characterization parameterTBDTBD  °C/W
RθJC(bot)Junction-to-case (bottom) thermal resistanceTBDTBD  °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.