JAJSJP7C April   2011  – March 2021 OPA2376-Q1 , OPA376-Q1 , OPA4376-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA376-Q1
    5. 6.5 Thermal Information: OPA2376-Q1
    6. 6.6 Thermal Information: OPA4376-Q1
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Input Offset Voltage and Input Offset Voltage Drift
      3. 7.3.3 Capacitive Load and Stability
      4. 7.3.4 Common-Mode Voltage Range
      5. 7.3.5 Input and ESD Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Amplifier Configurations
      2. 8.1.2 Active Filtering
      3. 8.1.3 Driving an Analog-to-Digital Converter
      4. 8.1.4 Phantom-Powered Microphone
      5. 8.1.5 Speech Bandpass-Filtered Data Acquisition System
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI™ Simulation Software (Free Download)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH® Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-05D6EBA2-2FE7-41B9-8C98-D2E2F530AA1D-low.gifFigure 5-1 OPA376-Q1: DBV (5-Pin SOT-23) Package, Top View
GUID-0B232E01-A124-4F9A-BD0F-729B7DC8BDF9-low.gif
(1) NC denotes no internal connection.
Figure 5-3 OPA376-Q1: D (8-Pin SOIC) Package, Top View
GUID-59F947E4-1BBF-4FED-A106-A364F6244450-low.gifFigure 5-2 OPA376-Q1: DCK (5-Pin SC70) Package, Top View
Table 5-1 Pin Functions: OPA376-Q1
PIN I/O DESCRIPTION
NAME NO.
SOT-23 SC70 SOIC
+IN 3 1 3 I Noninverting input+
–IN 4 3 2 I Inverting input–
NC — — 1, 5, 8 — No internal connection
OUT 1 4 6 O Output
V+ 5 5 7 — Positive (highest) power supply+
V– 2 2 4 — Negative (lowest) power supply–
GUID-53DBB879-58D2-4F83-B37B-7BE87C59ECC7-low.gif Figure 5-4 OPA2376-Q1: D (8-Pin SOIC) and DGK (8-Pin VSSOP) Packages, Top View
Table 5-2 Pin Functions: OPA2376-Q1
PIN I/O DESCRIPTION
NAME NO.
+IN A 3 I Noninverting input, channel A+
–IN A 2 I Inverting input, channel A–
+IN B 5 I Noninverting input, channel B+
–IN B 6 I Inverting input, channel B–
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
V– 4 — Negative (lowest) power supply
V+ 8 — Positive (highest) power supply
GUID-33126F3F-DFAE-4EB4-838E-9C7BA5A92B72-low.gif Figure 5-5 OPA4376-Q1: PW (14-Pin TSSOP) Package, Top View
Table 5-3 Pin Functions: OPA4376-Q1
PIN I/O DESCRIPTION
NAME NO.
+IN A 3 I Noninverting input, channel A+
–IN A 2 I Inverting input, channel A–
+IN B 5 I Noninverting input, channel B+
–IN B 6 I Inverting input, channel B–
+IN C 10 I Noninverting input, channel C+
–IN C 9 I Inverting input, channel C–
+IN D 12 I Noninverting input, channel D+
–IN D 13 I Inverting input, channel D–
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
OUT C 8 O Output, channel C
OUT D 14 O Output, channel D
V+ 4 — Positive (highest) power supply
V– 11 — Negative (lowest) power supply