JAJSOE0A May   2022  – August 2022 OPA3S2859

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Programmable Gain
      2. 8.3.2 Slew Rate
      3. 8.3.3 Input and ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply and Single-Supply Operation
      2. 8.4.2 Power-Down Mode
      3. 8.4.3 Gain Select Mode (SEL)
      4. 8.4.4 Latch Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 RTW Package,
24-Pin WQFN With Exposed Thermal Pad
(Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
COM_A 23 I Photodiode input – Channel A
COM_B 8 I Photodiode input – Channel B
FB_A0 20 I Feedback connection to Channel A – TIA Gain Resistor (Low gain, optimized for gain in < 10 kΩ range)
FB_A1 21 I

Feedback connection to Channel A – TIA Gain Resistor
(Mid gain, optimized for gain in 10 kΩ – 100 kΩ range)
FB_A2 22 I Feedback connection to Channel A – TIA Gain Resistor (High gain, optimized for gain in > 100 kΩ range)
FB_B0 11 I Feedback connection to Channel B – TIA Gain Resistor (Low gain, optimized for gain in < 10 kΩ range)
FB_B1 10 I

Feedback connection to Channel B – TIA Gain Resistor
(Mid gain, optimized for gain in 10 kΩ – 100 kΩ range)
FB_B2 9 I Feedback connection to Channel B – TIA Gain Resistor (High gain, optimized for gain in > 100 kΩ range)
INA- 24 I Negative (inverting) input for amplifier A
INA+ 1 I Positive (noninverting) input for amplifier A
INB- 7 I Negative (inverting) input for amplifier B
INB+ 6 I Positive (noninverting) input for amplifier B
LTCH_A 3 I

Latch control input for Channel A. LTCH_A = logic high (default) = transparent mode, gain setting changes based on SEL0 and SEL1 pins are reflected at the output.
LTCH_A = logic low = latch mode = changing SEL0 and SEL1 pins does not affect the gain configuration of amplifier.
LTCH_B 4 I

Latch control input for Channel B. LTCH_B = logic high (default) = transparent mode, gain setting changes based on SEL0 and SEL1 pins are reflected at the output.
LTCH_B = logic low = latch mode = changing SEL0 and SEL1 pins does not affect the gain configuration of amplifier.
PD 15 I Power down pin. PD = logic high (default) = normal operation, PD = logic low = power down mode.
SEL0 5 I TIA gain selection. SEL0 = logic high (default). See Table 5-2 for details.
SEL1 2 I TIA gain selection. SEL1 = logic high (default). See Table 5-2 for details.
VOUT_A 19 O Output of amplifier A
VOUT_B 12 O Output of amplifier B
VS- 13, 18 I Negative (lowest) power supply
VS+ 14, 16, 17 I Positive (highest) power supply
Thermal pad — Connect the thermal pad to the most negative power supply (pin 13 and 18) of the device under test (DUT).
(1) I = input, O = output
Table 5-2 Select Pin Decoder
SEL1 SEL0 Gain
LOW HIGH Low Gain, optimized for gain in < 10 kΩ range
LOW LOW Mid Gain, optimized for gain in 10 kΩ – 100 kΩ range
HIGH LOW High Gain, optimized for gain in > 100 kΩ range
HIGH (Default) HIGH (Default) External Gain. All internal switches open