OPA3S2859 features LTCH_A and LTCH_B pins which independently latch the gain configuration for Channel A and Channel B, respectively. If the latch control inputs are connected to logic high or floating, then the chosen feedback selection (through the SEL0 and SEL1 pins) applies to A and B analog channels immediately, this is also called transparent mode. If the latch control inputs are logic low, then changing the feedback selection (through the SEL0 and SEL1 pins) does not affect the gain configuration of the respective amplifier channel. Figure 8-1 shows the minimum timing requirements that should be met when using LTCH_x pins to latch gain configuration.

As shown in Figure 8-1, use the latch control input for each channel to separately control the feedback selection from the common SEL1 and SEL0 pins. The latch control inputs can also provide benefits in some cases where channel A and B need to have the same configuration. For example, any timing skew from SEL1 and SEL0 may result in unintended switch logic configurations for a short-duration resulting in transient output glitch when switching between different settings in transparent mode. Holding the LTCH_x pin low until the new selection value at the SEL pins have settled can minimize these intermediate glitch states.

This feature is also useful in larger systems with multiple OPA3S2859 devices. The gain path can be set using common SEL0 and SEL1 signals for all the devices, and latch pins can be used to control the gain independently for each amplifier channel.

The steps to update the gain settings in the following example configuration for Channel A only, are as follows:

1. Set LTCH_B to logic low (latch mode), this way changes made on Channel A do not affect Channel B gain configuration.
2. If LTCH_A is high (transparent mode), then use SEL0 and SEL1 pins to select the feedback network of interest. If LTCH_A is low, then toggle it to logic high and use SEL0 and SEL1 pins to select the feedback network of interest.
3. To hold the selected gain, set LTCH_A to logic low. Ensure minimum setup time requirements (100 ns) are met between SELx selection to LTCH_A going low. Also, ensure that during the hold time (100 ns), no changes should be made on SELx pins. The minimum timing is based on internal device configuration. If needed, additional time must be added due to board layout parasitics and signal delays.
4. Gain setting for channel A is now latched and any changes on the SELx pins will not change the gain configuration for channel A.