The OPAx192 family (OPA192, OPA2192, and OPA4192) is a new generation of 36-V, e-trim operational amplifiers.
These devices offer outstanding dc precision and ac performance, including rail-to-rail input/output, low offset (±5 µV, typ), low offset drift (±0.2 µV/°C, typ), and 10-MHz bandwidth.
Unique features such as differential input-voltage range to the supply rail, high output current (±65 mA), high capacitive load drive of up to 1 nF, and high slew rate (20 V/µs) make the OPA192 a robust, high-performance operational amplifier for high-voltage industrial applications.
The OPA192 family of op amps is available in standard packages and is specified from –40°C to +125°C.
Changes from D Revision (September 2015) to E Revision
Changes from C Revision (March 2015) to D Revision
Changes from B Revision (March 2014) to C Revision
Changes from A Revision (January 2014) to B Revision
Changes from * Revision (December 2013) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | OPA192 | |||
D (SOIC), DGK (VSSOP) |
DBV (SOT) | |||
+IN | 3 | 3 | I | Noninverting input |
–IN | 2 | 4 | I | Inverting input |
NC | 1, 5, 8 | — | — | No internal connection (can be left floating) |
OUT | 6 | 1 | O | Output |
V+ | 7 | 5 | — | Positive (highest) power supply |
V– | 4 | 2 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | OPA2192 | OPA4192 | ||
D (SOIC), DGK (VSSOP) |
D (SOIC), PW (TSSOP) |
|||
+IN A | 3 | 3 | I | Noninverting input, channel A |
+IN B | 5 | 5 | I | Noninverting input, channel B |
+IN C | — | 10 | I | Noninverting input, channel C |
+IN D | — | 12 | I | Noninverting input, channel D |
–IN A | 2 | 2 | I | Inverting input, channel A |
–IN B | 6 | 6 | I | Inverting input, channel B |
–IN C | — | 9 | I | Inverting input,,channel C |
–IN D | — | 13 | I | Inverting input, channel D |
OUT A | 1 | 1 | O | Output, channel A |
OUT B | 7 | 7 | O | Output, channel B |
OUT C | — | 8 | O | Output, channel C |
OUT D | — | 14 | O | Output, channel D |
V+ | 8 | 4 | — | Positive (highest) power supply |
V– | 4 | 11 | — | Negative (lowest) power supply |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Supply voltage, VS = (V+) – (V–) | ±20 (40, single supply) |
V | |||
Signal input pins | Voltage | Common-mode | (V–) – 0.5 | (V+) + 0.5 | V |
Differential | (V+) – (V–) + 0.2 | ||||
Current | ±10 | mA | |||
Output short circuit(2) | Continuous | ||||
Temperature | Operating range | –55 | 150 | °C | |
Junction | 150 | ||||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
OPA192 | ||||
V(ESD) | Electrostatic discharge | Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | V |
OPA2192 | ||||
V(ESD) | Electrostatic discharge | Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 | V |
OPA4192 | ||||
V(ESD) | Electrostatic discharge | Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Supply voltage, VS = (V+) – (V–) | 4.5 (±2.25) | 36 (±18) | V | ||
Specified temperature | –40 | +125 | °C |
THERMAL METRIC(1) | OPA192 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | DBV (SOT) | DGK (VSSOP) | |||
8 PINS | 5 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 115.8 | 158.8 | 180.4 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 60.1 | 60.7 | 67.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 56.4 | 44.8 | 102.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 12.8 | 1.6 | 10.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 55.9 | 4.2 | 100.3 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | N/A | N/A | N/A | °C/W |
THERMAL METRIC(1) | OPA2192 | UNIT | ||
---|---|---|---|---|
D (SOIC) | DGK (VSSOP) | |||
8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 107.9 | 158 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 53.9 | 48.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 48.9 | 78.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 6.6 | 3.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 48.3 | 77.3 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | N/A | N/A | °C/W |
THERMAL METRIC(1) | OPA4192 | UNIT | ||
---|---|---|---|---|
D (SOIC) | PW (TSSOP) | |||
14 PINS | 14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 86.4 | 92.6 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 46.3 | 27.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 41.0 | 33.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 11.3 | 1.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 40.7 | 33.1 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | N/A | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | |||||||
VOS | Input offset voltage | ±5 | ±25 | µV | |||
TA = 0°C to 85°C | ±8 | ±50 | |||||
TA = –40°C to +125°C | ±10 | ±75 | |||||
VCM = (V+) – 1.5 V | ±10 | ±40 | |||||
TA = 0°C to 85°C | ±25 | ±150 | |||||
TA = –40°C to +125°C | ±50 | ±250 | |||||
dVOS/dT | Input offset voltage drift | D packages only | TA = 0°C to 85°C | ±0.1 | ±0.5 | µV/°C | |
TA = –40°C to +125°C | ±0.15 | ±0.8 | |||||
DBV, DGK, and PW packages only | TA = 0°C to 85°C | ±0.1 | ±0.8 | ||||
TA = –40°C to +125°C | ±0.2 | ±1.0 | |||||
PSRR | Power-supply rejection ratio | TA = –40°C to +125°C | ±0.3 | ±1.0 | µV/V | ||
INPUT BIAS CURRENT | |||||||
IB | Input bias current | ±5 | ±20 | pA | |||
TA = –40°C to +125°C | ±5 | nA | |||||
IOS | Input offset current | ±2 | ±20 | pA | |||
TA = –40°C to +125°C | ±2 | nA | |||||
NOISE | |||||||
En | Input voltage noise | (V–) – 0.1 V < VCM < (V+) – 3 V | f = 0.1 Hz to 10 Hz | 1.30 | µVPP | ||
(V+) – 1.5 V < VCM < (V+) + 0.1 V | f = 0.1 Hz to 10 Hz | 4 | |||||
en | Input voltage noise density | (V–) – 0.1 V < VCM < (V+) – 3 V | f = 100 Hz | 10.5 | nV/√Hz | ||
f = 1 kHz | 5.5 | ||||||
(V+) – 1.5 V < VCM < (V+) + 0.1 V | f = 100 Hz | 32 | |||||
f = 1 kHz | 12.5 | ||||||
NOISE (continued) | |||||||
in | Input current noise density | f = 1 kHz | 1.5 | fA/√Hz | |||
INPUT VOLTAGE | |||||||
VCM | Common-mode voltage range | (V–) – 0.1 | (V+) + 0.1 | V | |||
CMRR | Common-mode rejection ratio | (V–) – 0.1 V < VCM < (V+) – 3 V | 120 | 140 | dB | ||
TA = –40°C to +125°C | 114 | 126 | |||||
(V+) – 1.5 V < VCM < (V+) | 100 | 120 | |||||
TA = –40°C to +125°C | 86 | 100 | |||||
(V+) – 3 V < VCM < (V+) – 1.5 V | See Typical Characteristics | ||||||
INPUT IMPEDANCE | |||||||
ZID | Differential | 100 || 1.6 | MΩ || pF | ||||
ZIC | Common-mode | 1 || 6.4 | 1013Ω || pF | ||||
OPEN-LOOP GAIN | |||||||
AOL | Open-loop voltage gain | (V–) + 0.6 V < VO < (V+) – 0.6 V, RLOAD = 2 kΩ | 120 | 134 | dB | ||
TA = –40°C to +125°C | 114 | 126 | |||||
(V–) + 0.3 V < VO < (V+) – 0.3 V, RLOAD = 10 kΩ | 126 | 140 | |||||
TA = –40°C to +125°C | 120 | 134 | |||||
FREQUENCY RESPONSE | |||||||
GBW | Unity gain bandwidth | 10 | MHz | ||||
SR | Slew rate | G = 1, 10-V step | 20 | V/µs | |||
ts | Settling time | To 0.01% | V S = ±18 V, G = 1, 10-V step | 1.4 | µs | ||
V S = ±18 V, G = 1, 5-V step | 0.9 | ||||||
To 0.001% | V S = ±18 V, G = 1, 10-V step | 2.1 | |||||
V S = ±18 V, G = 1, 5-V step | 1.8 | ||||||
tOR | Overload recovery time | VIN × G = VS | 200 | ns | |||
THD+N | Total harmonic distortion + noise | G = 1, f = 1 kHz, VO = 3.5 VRMS | 0.00008% | ||||
Crosstalk | OPA2192 and OPA4192, at dc | 150 | dB | ||||
OPA2192 and OPA4192, f = 100 kHz | 130 | ||||||
OUTPUT | |||||||
VO | Voltage output swing from rail | Positive rail | No load | 5 | 15 | mV | |
RLOAD = 10 kΩ | 95 | 110 | |||||
RLOAD = 2 kΩ | 430 | 500 | |||||
Negative rail | No load | 5 | 15 | ||||
RLOAD = 10 kΩ | 95 | 110 | |||||
RLOAD = 2 kΩ | 430 | 500 | |||||
ISC | Short-circuit current | ±65 | mA | ||||
CLOAD | Capacitive load drive | See Typical Characteristics | |||||
ZO | Open-loop output impedance | f = 1 MHz, IO = 0 A, see Figure 31 | 375 | Ω | |||
POWER SUPPLY | |||||||
IQ | Quiescent current per amplifier | IO = 0 A | 1 | 1.2 | mA | ||
TA = –40°C to +125°C, IO = 0 A | 1.5 | ||||||
TEMPERATURE | |||||||
Thermal protection(1) | 140 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | |||||||
VOS | Input offset voltage | VCM = (V+) – 3 V | ±5 | ±25 | µV | ||
TA = 0°C to 85°C | ±8 | ±50 | |||||
TA = –40°C to +125°C | ±10 | ±75 | |||||
(V+) – 3.5 V < VCM < (V+) – 1.5 V | See Common-Mode Voltage Range section | ||||||
VCM = (V+) – 1.5 V | ±10 | ±40 | µV | ||||
TA = 0°C to 85°C | ±25 | ±150 | |||||
TA = –40°C to +125°C | ±50 | ±250 | |||||
dVOS/dT | Input offset voltage drift | VCM = (V+) – 3 V, D packages only |
TA = 0°C to 85°C | ±0.1 | ±0.5 | µV/°C | |
TA = –40°C to +125°C | ±0.15 | ±0.8 | |||||
VCM = (V+) – 3 V, DBV, DGK, and PW packages only |
TA = 0°C to 85°C | ±0.1 | ±0.8 | ||||
TA = –40°C to +125°C | ±0.2 | ±1.1 | |||||
VCM = (V+) – 1.5 V, TA = –40°C to +125°C | ±0.5 | ±3 | |||||
PSRR | Power-supply rejection ratio | TA = –40°C to +125°C, VCM = VS / 2 – 0.75 V | ±1 | µV/V | |||
INPUT BIAS CURRENT | |||||||
IB | Input bias current | ±5 | ±20 | pA | |||
TA = –40°C to +125°C | ±5 | nA | |||||
IOS | Input offset current | ±2 | ±20 | pA | |||
TA = –40°C to +125°C | ±2 | nA | |||||
NOISE | |||||||
En | Input voltage noise | (V–) – 0.1 V < VCM < (V+) – 3 V, f = 0.1 Hz to 10 Hz | 1.30 | µVPP | |||
(V+) – 1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz | 4 | ||||||
en | Input voltage noise density | (V–) – 0.1 V < VCM < (V+) – 3 V | f = 100 Hz | 10.5 | nV/√Hz | ||
f = 1 kHz | 5.5 | ||||||
(V+) – 1.5 V < VCM < (V+) + 0.1 V | f = 100 Hz | 32 | |||||
f = 1 kHz | 12.5 | ||||||
in | Input current noise density | f = 1 kHz | 1.5 | fA/√Hz | |||
INPUT VOLTAGE | |||||||
VCM | Common-mode voltage range | (V–) – 0.1 | (V+) + 0.1 | V | |||
CMRR | Common-mode rejection ratio | (V–) – 0.1 V < VCM < (V+) – 3 V | 94 | 110 | dB | ||
TA = –40°C to +125°C | 90 | 104 | |||||
(V+) – 1.5 V < VCM < (V+) | 100 | 120 | |||||
TA = –40°C to +125°C | 84 | 100 | |||||
(V+) – 3 V < VCM < (V+) – 1.5 V | See Typical Characteristics | ||||||
INPUT IMPEDANCE | |||||||
ZID | Differential | 100 || 1.6 | MΩ || pF | ||||
ZIC | Common-mode | 1 || 6.4 | 1013Ω || pF | ||||
OPEN-LOOP GAIN | |||||||
AOL | Open-loop voltage gain | (V–) + 0.6 V < VO < (V+) – 0.6 V, RLOAD = 2 kΩ | 110 | 120 | dB | ||
TA = –40°C to +125°C | 100 | 114 | |||||
(V–) + 0.3 V < VO < (V+) – 0.3 V, RLOAD = 10 kΩ | 110 | 126 | |||||
TA = –40°C to +125°C | 110 | 120 | |||||
FREQUENCY RESPONSE | |||||||
GBW | Unity gain bandwidth | 10 | MHz | ||||
SR | Slew rate | G = 1, 10-V step | 20 | V/µs | |||
ts | Settling time | To 0.01% | VS = ±3 V, G = 1, 5-V step | 1 | µs | ||
tOR | Overload recovery time | VIN× G = VS | 200 | ns | |||
Crosstalk | OPA2192 and OPA4192, at dc | 150 | dB | ||||
OPA2192 and OPA4192, f = 100 kHz | 130 | ||||||
OUTPUT | |||||||
VO | Voltage output swing from rail | Positive rail | No load | 5 | 15 | mV | |
RLOAD = 10 kΩ | 95 | 110 | |||||
RLOAD = 2 kΩ | 430 | 500 | |||||
Negative rail | No load | 5 | 15 | ||||
RLOAD = 10 kΩ | 95 | 110 | |||||
RLOAD = 2 kΩ | 430 | 500 | |||||
ISC | Short-circuit current | ±65 | mA | ||||
CLOAD | Capacitive load drive | See Typical Characteristics | |||||
ZO | Open-loop output impedance | f = 1 MHz, IO = 0 A, see Figure 31 | 375 | Ω | |||
POWER SUPPLY | |||||||
IQ | Quiescent current per amplifier | IO = 0 A | 1 | 1.2 | mA | ||
TA = –40°C to +125°C | 1.5 | ||||||
TEMPERATURE | |||||||
Thermal protection(1) | 140 | °C |
DESCRIPTION | FIGURE |
---|---|
Offset Voltage Production Distribution | Figure 1 to Figure 6 |
Offset Voltage Drift Distribution | Figure 7 to Figure 10 |
Offset Voltage vs Temperature | Figure 11 |
Offset Voltage vs Common-Mode Voltage | Figure 12 to Figure 14 |
Offset Voltage vs Power Supply | Figure 15 |
Open-Loop Gain and Phase vs Frequency | Figure 16 |
Closed-Loop Gain and Phase vs Frequency | Figure 17 |
Input Bias Current vs Common-Mode Voltage | Figure 18 |
Input Bias Current vs Temperature | Figure 19 |
Output Voltage Swing vs Output Current (maximum supply) | Figure 20 |
CMRR and PSRR vs Frequency | Figure 21 |
CMRR vs Temperature | Figure 22 |
PSRR vs Temperature | Figure 23 |
0.1-Hz to 10-Hz Noise | Figure 24 |
Input Voltage Noise Spectral Density vs Frequency | Figure 25 |
THD+N Ratio vs Frequency | Figure 26 |
THD+N vs Output Amplitude | Figure 27 |
Quiescent Current vs Supply Voltage | Figure 28 |
Quiescent Current vs Temperature | Figure 29 |
Open Loop Gain vs Temperature | Figure 30 |
Open Loop Output Impedance vs Frequency | Figure 31 |
Small Signal Overshoot vs Capacitive Load (100-mV Output Step) | Figure 32, Figure 33 |
No Phase Reversal | Figure 34 |
Positive Overload Recovery | Figure 35 |
Negative Overload Recovery | Figure 36 |
Small-Signal Step Response (100 mV) | Figure 37, Figure 38 |
Large-Signal Step Response | Figure 39 |
Settling Time | Figure 40 to Figure 43 |
Short-Circuit Current vs Temperature | Figure 44 |
Maximum Output Voltage vs Frequency | Figure 45 |
Propagation Delay Rising Edge | Figure 46 |
Propagation Delay Falling Edge | Figure 47 |
Crosstalk vs Frequency | Figure 48 |
OPA192ID and OPA2192ID |
OPA192ID and OPA2192ID |
OPA192IDBV, OPA192IDGK, OPA2192IDGK, and OPA4192IPW |
OPA192IDBV, OPA192IDGK, OPA2192IDGK, and OPA4192IPW |
The OPAx192 family of operational amplifiers is manufactured using TI’s e-trim technology. Each amplifier input offset voltage and input offset voltage drift is trimmed in production, thereby minimizing errors associated with input offset voltage and input offset voltage drift. The e-trim technology is a TI proprietary method of trimming internal device parameters during either wafer probing or final testing. When trimming input offset voltage drift the systematic or linear drift error on each device is trimmed to zero. This results in the remaining errors associated with input offset drift are minimal and are the result from only nonlinear error sources. Figure 49 illustrates this concept.
A common method of specifying input offset voltage drift is the box method. The box method estimates a maximum input offset drift by bounding the offset voltage versus temperature curve with a box and using the corners of this bounding box to determine the drift. The slope of the line connecting the diagonal corners of the box corresponds to the input offset voltage drift. Figure 50 shows the box method concept. The box method works particularly well when the input offset drift is dominated by the linear component of drift, but because the OPA192 family uses TI’s e-trim technology to remove the linear component input offset voltage drift, the box method is not a particularly useful method of accurately performing an error analysis. Figure 50 shows 30 typical units of the OPAx192 with the box method superimposed for illustrative purposes. The boundaries of the box are determined by the specified temperature range along the x-axis and the maximum specified input offset voltage across that same temperature range along the y-axis. Using the box method predicts an input offset voltage drift of 0.9 µV/°C. As shown in Figure 50, the slopes of the actual input offset voltage versus temperature are much less than that predicted by the box method. The box method predicts a pessimistic value for the maximum input offset voltage drift and is not recommended when performing an error analysis.
Instead of the box method, a convenient way to illustrate input offset drift is to compute the slopes of the input offset voltage versus temperature curve. This is the same as computing the input offset drift at each point along the input offset voltage versus temperature curve. The results for the OPAx192 family are shown in Figure 51 and Figure 52.
As shown in Figure 51, the input offset drift is typically less than ±0.3 µV/°C over the range from –40°C to +125°C. When performing an error analysis over the full specified temperature range, use the typical and maximum values for input offset voltage drift as described in the Electrical Characteristics tables. If a reduced temperature range is applicable, use the information shown in Figure 51 or Figure 52 when performing an error analysis. To determine the change in input offset voltage, use Equation 1:
where
For example, determine the amount of OPA192ID input offset voltage change over the temperature range of 25°C to 75°C for 1 σ (68%) of the units. As shown in Figure 51, the input offset drift is typically 0.15 µV/°C. This input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.15 µV/°C = 7.5 µV .
For 3 σ (99.7%) of the units, Figure 51 shows a typical input offset drift of 0.4 µV/°C. This input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.4 µV/°C = 20 µV.
Figure 53 shows six typical units.
The OPAx192 family of operational amplifiers use e-trim, a method of package-level trim for offset and offset temperature drift implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points are set, further communication to the trim structure is permanently disabled. The Functional Block Diagram section shows the simplified diagram of the OPA192 with e-trim.
Unlike previous e-trim op amps, the OPAx192 uses a patented two-temperature trim architecture to achieve a very low offset voltage of 25 µV (max) and low voltage offset drift of 0.5 µV/°C (max) over the full specified temperature range. This level of precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial sensors, filters, and high-voltage data acquisition.
The OPAx192 uses a unique input architecture to eliminate the need for input protection diodes but still provides robust input protection under transient conditions. Conventional input diode protection schemes shown in Figure 54 can be activated by fast transient step responses and can introduce signal distortion and settling time delays because of alternate current paths, as shown in Figure 55. For low-gain circuits, these fast-ramping input signals forward-bias back-to-back diodes, causing an increase in input current, and resulting in extended settling time, as shown in Figure 56.
The OPAx192 family of operational amplifiers provides a true high-impedance differential input capability for high-voltage applications. This patented input protection architecture does not introduce additional signal distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications. The OPA192 can tolerate a maximum differential swing (voltage between inverting and noninverting pins of the op amp) of up to 36 V, making the device suitable for use as a comparator or in applications with fast-ramping input signals such as multiplexed data-acquisition systems; see Figure 66.
The OPAx192 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx192 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 57 shows the results of this testing on the OPA192. Table 2 shows the EMIRR IN+ values for the OPA192 at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be centered on or operated near the particular frequency shown. Detailed information can also be found in the application report EMI Rejection Ratio of Operational Amplifiers, SBOA128, available for download from www.ti.com.
FREQUENCY | APPLICATION OR ALLOCATION | EMIRR IN+ |
---|---|---|
400 MHz | Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications | 44.1 dB |
900 MHz | Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications | 52.8 dB |
1.8 GHz | GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) | 61.0 dB |
2.4 GHz | 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) | 69.5 dB |
3.6 GHz | Radiolocation, aero communication and navigation, satellite, mobile, S-band | 88.7 dB |
5.0 GHz | 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) | 105.5 dB |
The OPAx192 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The OPAx192 is a rail-to-rail input op amp; therefore, the common-mode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into the appropriate rail. This performance is shown in Figure 58.
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This phenomenon is called self heating. The absolute maximum junction temperature of the OPAx192 is 150°C. Exceeding this temperature causes damage to the device. The OPAx192 has a thermal protection feature that prevents damage from self heating. The protection works by monitoring the temperature of the device and turning off the op amp output drive for temperatures above 140°C. Figure 59 shows an application example for the OPA192 that has significant self heating (159°C) because of its power dissipation (0.81 W). Thermal calculations indicate that for an ambient temperature of 65°C the device junction temperature must reach 187°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 59 shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.
The OPAx192 features a patented output stage capable of driving large capacitive loads, and in a unity-gain configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 60 and Figure 61. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier will be stable in operation.
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
(10 Ω to 20 Ω) resistor, RISO, in series with the output, as shown in Figure 62. This resistor significantly reduces ringing and maintains dc performance for purely capacitive loads. However, if a resistive load is in parallel with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive makes the OPA192 well suited for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 62 uses an isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin, and results using the OPA192 are summarized in Table 3. For additional information on techniques to optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation, and test results.
PARAMETER | VALUE | |||||||||
---|---|---|---|---|---|---|---|---|---|---|
Capacitive Load | 100 pF | 1000 pF | 0.01 µF | 0.1 µF | 1 µF | |||||
Phase Margin | 45° | 60° | 45° | 60° | 45° | 60° | 45° | 60° | 45° | 60° |
RISO (Ω) | 47.0 | 360.0 | 24.0 | 100.0 | 20.0 | 51.0 | 6.2 | 15.8 | 2.0 | 4.7 |
Measured Overshoot (%) | 23.2 8.6 | 10.4 | 22.5 | 9.0 | 22.1 | 8.7 | 23.1 | 8.6 | 21.0 | 8.6 |
Calculated PM | 45.1° | 58.1° | 45.8° | 59.7° | 46.1° | 60.1° | 45.2° | 60.2° | 47.2° | 60.2° |
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For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results, refer to TI Precision Design TIDU032, Capacitive Load Drive Solution using an Isolation Resistor . |
The OPAx192 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and P-channel differential input pairs, as shown in Figure 63. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are on. This transition region can vary modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise and THD performance may be degraded compared to operation outside this region.
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when possible. The OPAx192 uses a precision trim for both the N-channel and P-channel regions. This technique enables significantly lower levels of offset than previous-generation devices, causing variance in the transition region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown in Figure 64.
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress (EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. Figure 65 shows an illustration of the ESD circuits contained in the OPAx192 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the OPAx192 is approximately 200 ns.
The OPAx192 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx192 is 36 V (±18 V).
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The OPAx192 family offers outstanding dc precision and ac performance. These devices operate up to 36-V supply rails and offer true rail-to-rail input/output, ultralow offset voltage and offset voltage drift, as well as
10-MHz bandwidth and high capacitive load drive. These features make the OPAx192 a robust, high-performance operational amplifier for high-voltage industrial applications.
Figure 66 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in industrial applications that require low distortion and a high-voltage differential input. The circuit uses the ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input. The design requirements for this block design are:
The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 66. The circuit is a multichannel data acquisition signal chain consisting of an input low-pass filter, multiplexer (mux), mux output buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit resolution and lowest distortion system. The diagram includes the most important specifications for each individual analog block.
This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding helps in the decision of an appropriate input filter and selection of a mux to meet the system settling requirements. The next important step is the design of the attenuating analog front-end (AFE) used to level translate the high-voltage input signal to a low-voltage ADC input when maintaining amplifier stability. The next step is to design a digital interface to switch the mux input channels with minimum delay. The final design challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage with low offset, drift, and noise contributions.
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For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High Voltage Inputs with Lowest Distortion. |
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages. By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high output current and slew rate of the OPAx192 make the device an optimal amplifier to achieve slew rate control for both dual- and single-supply systems.Figure 68 shows the OPA192 in a slew-rate limit design.
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For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp. |
The OPAx192 features high output current drive capability and low input offset voltage, making the device an excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the 10-µF ceramic capacitor shown in Figure 69, RISO, a 37.4-Ω isolation resistor, provides separation of two feedback paths for optimal stability. Feedback path number one is through RF and is directly at the output, VOUT. Feedback path number two is through RFx and CF and is connected at the output of the op amp. The optimized stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz and still provides a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability components: RF, RFx , CF , and RISO.