SBOS538F January   2011  – December 2016 OPA2322 , OPA322 , OPA4322

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA322, OPA322S
    5. 6.5 Thermal Information: OPA2322, OPA2322S
    6. 6.6 Thermal Information: OPA4322, OPA4322S
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Input and ESD Protection
      3. 7.3.3 Phase Reversal
      4. 7.3.4 Feedback Capacitor Improves Response
      5. 7.3.5 EMI Susceptibility and Input Filtering
      6. 7.3.6 Output Impedance
      7. 7.3.7 Capacitive Load and Stability
      8. 7.3.8 Overload Recovery Time
      9. 7.3.9 Shutdown Function
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Active Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Leadless DFN Package
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 TINA-TI™ (Free Software Download)
        2. 11.1.2.2 DIP Adapter EVM
        3. 11.1.2.3 Universal Operational Amplifier EVM
        4. 11.1.2.4 TI Precision Designs
        5. 11.1.2.5 WEBENCH Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

OPA322: DBV Package
5-Pin SOT-23
Top View
OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S po_sot23-5_bos513.gif
OPA322S: DBV Package
6-Pin SOT-23
Top View
OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S po_sot23-6_bos513.gif

Pin Functions: OPA322, OPA322S

PIN I/O DESCRIPTION
NAME OPA322 OPA322S
SOT-23 SOT-23
–IN 4 4 I Inverting input
+IN 3 3 I Noninverting input
OUT 1 1 O Output
SHDN — 5 I Shutdown control (active low)
V– 2 2 — Negative (lowest) power supply
V+ 5 6 — Positive (highest) power supply
OPA2322: D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S po_msop-8_bos538.gif
OPA2322: DRG Package
8-Pin SON
Top View
OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S po_dfn-8_bos538.gif
1. Connect thermal pad to V–.
2. Pad size: 2 mm × 1.2 mm.
OPA2322S: DGS Package
10-Pin VSSOP
Top View
OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S po_msop-10_bos538.gif

Pin Functions: OPA2322, OPA2322S

PIN I/O DESCRIPTION
NAME OPA2322 OPA2322S
SOIC,
VSSOP		 SON VSSOP
–IN A 2 2 2 I Inverting input, channel A
+IN A 3 3 3 I Noninverting input, channel A
–IN B 6 6 8 I Inverting input, channel B
+IN B 5 5 7 I Noninverting input, channel B
OUT A 1 1 — O Output, channel A
OUT B 7 7 — O Output, channel B
SHDN A — — 5 I Shutdown control, channel A (active low)
SHDN B — — 6 I Shutdown control, channel B (active low)
V– 4 4 4 — Negative (lowest) power supply
V+ 8 8 10 — Positive (highest) power supply
VOUT A — — 1 O Output, channel A
VOUT B — — 9 O Output, channel B
PW Package
14-Pin TSSOP
Top View
OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S po_tssop14_bos538.gif
PW Package
16-Pin TSSOP
Top View
OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S po_tssop16_bos538.gif

Pin Functions: OPA4322, OPA4322S

PIN I/O DESCRIPTION
NAME OPA4322 OPA4322S
TSSOP TSSOP
–IN A 2 2 I Inverting input, channel A
+IN A 3 3 I Noninverting input, channel A
–IN B 6 6 I Inverting input, channel B
+IN B 5 5 I Noninverting input, channel B
–IN C 9 11 I Inverting input, channel C
+IN C 10 12 I Noninverting input, channel C
–IN D 13 15 I Inverting input, channel D
+IN D 12 14 I Noninverting input, channel D
OUT A 1 1 O Output, channel A
OUT B 7 7 O Output, channel B
OUT C 8 10 O Output, channel C
OUT D 14 16 O Output, channel D
SHDN A/B — 8 I Shutdown control, channels A and B (active low)
SHDN C/D 9 I Shutdown control, channels C and D (active low)
V– 11 13 — Negative (lowest) power supply
V+ 4 4 — Positive (highest) power supply