JAJSC13F September   2003  – September 2016 OPA2373 , OPA2374 , OPA373 , OPA374 , OPA4374

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: OPA373
    5. 7.5  Thermal Information: OPA374
    6. 7.6  Thermal Information: OPA2373
    7. 7.7  Thermal Information: OPA2374
    8. 7.8  Thermal Information: OPA4374
    9. 7.9  Electrical Characteristics: VS = 2.7 V to 5.5 V
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Common-Mode Voltage Range
      3. 8.3.3 Rail-to-Rail Input
      4. 8.3.4 Rail-to-Rail Output
      5. 8.3.5 Capacitive Load and Stability
      6. 8.3.6 Enable or Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 Driving ADCs
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 VSON Package
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 TINA-TI™ (無料のダウンロード・ソフトウェア)
        2. 12.1.1.2 DIPアダプタ評価モジュール
        3. 12.1.1.3 ユニバーサル・オペアンプ評価モジュール
        4. 12.1.1.4 TI Precision Designs
        5. 12.1.1.5 WEBENCHFilter Designer
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

The leadframe die pad must be soldered to a thermal pad on the PCB. A mechanical data sheet showing an example layout is attached at the end of this data sheet. Refinements to this layout may be required based on assembly process requirements.

Mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are intended for use with thermal vias that connect the leadframe die pad to the heat sink area on the PCB. Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests.

Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.

11.1.1 VSON Package

The OPA2373 is available in a 10-pin VSON package, which is a VQFN package with lead contacts on only two sides of the bottom of the package. This leadless, near-chip-scale package maximizes board space and enhances thermal and electrical characteristics through an exposed pad. VSON packages are physically small, have a smaller routing area, improved thermal performance, and improved electrical parasitics, with a pinout scheme that is consistent with other commonly-used packages, such as SOIC and VSSOP. Additionally, the absence of external leads eliminates bent-lead issues.

The VSON package can be easily mounted using standard PCP assembly techniques. See QFN/SON PCB Attachment and Quad Flatpack No-Lead Logic Packages, both available for download at www.ti.com.

NOTE

The exposed leadframe die pad on the bottom of the package must be connected to V−.

11.2 Layout Example

OPA373 OPA374 OPA2373 OPA2374 OPA4374 layout_example_bos620.gif Figure 33. Operational Amplifier Board Layout for Noninverting Configuration