SBOS206F January   2001  – October 2023 OPA561

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Feature Description
      1. 6.2.1 Adjustable Current Limit
        1. 6.2.1.1 Current Limit Accuracy
        2. 6.2.1.2 Setting the Current Limit
      2. 6.2.2 Enable-Status (E/S) Pin
        1. 6.2.2.1 Output Disable
        2. 6.2.2.2 Maintaining Microcontroller Compatibility
      3. 6.2.3 Overcurrent Flag
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Output Stage Compensation
      2. 7.1.2 Output Protection
      3. 7.1.3 Thermal Protection
      4. 7.1.4 Power Dissipation
      5. 7.1.5 Heat-Sink Area
      6. 7.1.6 Amplifier Mounting
        1. 7.1.6.1 What is the PowerPAD™ Integrated Circuit Package?
        2. 7.1.6.2 PowerPAD™ Integrated Circuit Package Assembly Process
    2. 7.2 Typical Application
      1. 7.2.1 Laser Diode Driver
      2. 7.2.2 Programmable Power Supply
      3. 7.2.3 Power-Line Communication Modem
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PWP|20
サーマルパッド・メカニカル・データ
発注情報

7.1.6.2 PowerPAD™ Integrated Circuit Package Assembly Process

  1. Prepare the PCB with a top-side etch pattern, as shown in the attached Thermal Land Pattern mechanical drawing. Use etch for the leads as well as etch for the thermal land.
  2. Place the recommended number of holes (or thermal vias) in the area of the thermal pad as shown on the attached Land Pattern mechanical. Use holes that are 13 mils in diameter. Keep the holes small so that solder wicking through the holes is not a problem during reflow.
  3. Best practice is to place a small number of the holes under the package and outside the thermal pad area. These holes provide additional heat path between the copper land and ground plane and are 25 mils in diameter. The holes can be larger because the holes are not in the area to be soldered, so wicking is not a problem.
  4. Connect all holes, including those within the thermal pad area and outside the pad area, to the internal ground plane or other internal copper plane.
  5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology; see Figure 7-5. Web connections have a high thermal resistance that is useful for slowing the heat transfer during soldering operations. This heat-transfer slowing makes the soldering of vias that have plane connections easier. However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore, connect the holes under the PowerPAD package to the internal ground plane with a complete connection around the entire circumference of the plated through hole.
  6. On the top-side solder mask, leave exposed the terminals of the package and the thermal pad area. On the thermal pad area, leave the 13 mil holes exposed. Cover the larger 25 mil holes outside the thermal pad area with solder mask.
  7. Apply solder paste to the exposed thermal pad area and all of the package pins.
  8. With these preparatory steps in place, the PowerPAD IC package is simply placed in position and run through the solder reflow operation, as with any standard surface-mount component. This procedure results in a part that is properly installed.
For detailed information on the PowerPAD IC package, including thermal modeling considerations and repair procedures, see the PowerPAD Thermally Enhanced Package technical brief, available at www.ti.com.

GUID-20230614-SS0I-XZFX-VW5N-1L3V4269GTDX-low.svg Figure 7-5 Via Connection