JAJSVI0H December   2001  – October 2024 OPA690

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics OPA690IDBV, VS = ±5 V
    6. 6.6  Electrical Characteristics OPA690IDBV, VS = 5 V
    7. 6.7  Electrical Characteristics OPA690ID, VS = ±5 V
    8. 6.8  Electrical Characteristics OPA690ID, VS = 5 V
    9. 6.9  Typical Characteristics: OPA690IDBV, VS = ±5V
    10. 6.10 Typical Characteristics: OPA690IDBV, VS = 5V
    11. 6.11 Typical Characteristics: OPA690ID, VS = ±5V
    12. 6.12 Typical Characteristics: OPA690ID, VS = 5V
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wideband Voltage-Feedback Operation
      2. 7.3.2 Input and ESD Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bandwidth Versus Gain: Noninverting Operation
      2. 8.1.2 Inverting Amplifier Operation
      3. 8.1.3 Optimizing Resistor Values
      4. 8.1.4 Output Current and Voltage
      5. 8.1.5 Driving Capacitive Loads
      6. 8.1.6 Distortion Performance
      7. 8.1.7 Noise Performance
      8. 8.1.8 DC Accuracy and Offset Control
      9. 8.1.9 Thermal Analysis
    2. 8.2 Typical Applications
      1. 8.2.1 High-Performance DAC Transimpedance Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Single-Supply Active Filters
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curve
      3. 8.2.3 High-Power Line Driver
        1. 8.2.3.1 Design Requirements
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Macromodels and Applications Support
      2. 9.1.2 Demonstration Fixtures
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.2 Detailed Design Procedure

In this circuit, only one side of the complementary output drive signal is used. Figure 8-6 shows the signal output current connected into the virtual ground summing junction of the OPA690, which is set up as a transimpedance stage or I-V converter. The unused current output of the DAC is connected to ground. If the DAC requires that the outputs terminate to a compliance voltage other than ground for operation, the appropriate voltage level can be applied to the noninverting input of the OPA690. The dc gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance produces a zero in the noise gain for the OPA690 that can cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise gain peaking. To achieve a flat transimpedance frequency response, set the pole in the feedback network to Equation 6.

Equation 6. OPA690

Equation 6 gives a closed-loop transimpedance bandwidth, f−3dB, of approximately Equation 7.

Equation 7. OPA690

where

  • GBP = gain bandwidth product (Hz) for the OPA690