One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that can be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA690 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series-isolation resistor between the amplifier output and the capacitive load. This configuration does not eliminate the pole from the loop response, but rather shifts the pole and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability.

The typical characteristics show the recommended R_S versus capacitive load (Figure 6-51 for ±5 V and Figure 6-66 for 5 V), and the resulting frequency response at the load. Parasitic capacitive loads greater than 2 pF can begin to degrade the performance of the OPA690. Long PCB traces, unmatched cables, and connections to multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA690 output pin (see Section 8.4.1).

The criterion for setting this R_S resistor is a maximum bandwidth, flat frequency response at the load. For the OPA690 operating in a gain of 2, the frequency response at the output pin is already slightly peaked without the capacitive load requiring relatively high values of R_S to flatten the response at the load. Increasing the noise gain reduces the peaking as described previously. The circuit of Figure 8-2 demonstrates this technique, allowing lower values of R_S to be used for a given capacitive load.

Figure 8-2 Capacitive Load Driving With Noise Gain Tuning

This gain of 2 V/V circuit includes a noise gain tuning resistor across the two inputs to increase the noise gain, increasing the unloaded phase margin for the op amp. Although this technique reduces the required R_S resistor for a given capacitive load, this technique does increase the noise at the output. This technique also decreases the loop gain, slightly decreasing the distortion performance. If, however, the dominant distortion mechanism arises from a high R_S value, significant dynamic range improvement can be achieved using this technique. Figure 8-3 shows the required R_S versus C_LOAD parametric on noise gain using this technique. This is the circuit of Figure 8-2 with R_NG adjusted to increase the noise gain (increasing the phase margin) then sweeping C_LOAD and finding the required R_S to get a flat frequency response. This plot also gives the required R_S versus C_LOAD for the OPA690 operated at higher signal gains.

Figure 8-3 Required R_S vs Noise Gain