JAJSP64I December   2003  – October 2024 OPA695

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics VS = ±5 V, OPA695ID, OPA695IDBV
    6. 5.6  Electrical Characteristics VS = 5 V, OPA695ID, OPA695IDBV
    7. 5.7  Electrical Characteristics VS = ±5 V, OPA695IDGK
    8. 5.8  Electrical Characteristics VS = 5 V, OPA695IDGK
    9. 5.9  Typical Characteristics: VS = ±5 V, OPA695IDBV, OPA695ID
    10. 5.10 Typical Characteristics: VS = 5 V, OPA695IDBV, OPA695ID
    11. 5.11 Typical Characteristics: VS = ±5 V, OPA695IDGK
    12. 5.12 Typical Characteristics: VS = 5 V, OPA695IDGK
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Wideband Current-Feedback Operation
      2. 6.3.2 Input and ESD Protection
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Operating Suggestions
        1. 7.1.1.1 Setting Resistor Values to Optimize Bandwidth
        2. 7.1.1.2 Output Current and Voltage
        3. 7.1.1.3 Driving Capacitive Loads
        4. 7.1.1.4 Distortion Performance
        5. 7.1.1.5 Noise Performance
        6. 7.1.1.6 Thermal Analysis
      2. 7.1.2 LO Buffer Amplifier
      3. 7.1.3 Wideband Cable Driving Applications
        1. 7.1.3.1 Cable Modem Return Path Driver
        2. 7.1.3.2 Arbitrary Waveform Driver
      4. 7.1.4 Differential I/O Applications
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Saw Filter Buffer
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Design-In Tools
        1. 8.1.1.1 Demonstration Fixtures
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Differential I/O Applications

The OPA695 offers very low 3rd-order distortion terms with a dominant 2nd-order distortion for the single amplifier operation. For the lowest distortion, particularly where differential outputs are needed, operating two OPA695 devices in a differential I/O design suppresses these even-order terms, delivering extremely low harmonic distortion through high frequencies and powers. Differential outputs are often preferred for high-performance ADCs, twisted-pair driving, and mixer interfaces. Two basic approaches to differential I/Os are the noninverting or inverting configurations. Because the output is differential, the signal polarity is somewhat meaningless; the noninverting and inverting terminology applies here to where the input is brought into the two OPA695s. Each approach has advantages and disadvantages. Figure 7-8 shows a basic starting point for noninverting differential I/O applications.

OPA695 Noninverting Input Differential I/O AmplifierFigure 7-8 Noninverting Input Differential I/O Amplifier

This approach allows for a source termination impedance independent of the signal gain. For instance, simple differential filters can be included in the signal path directly to the noninverting inputs without interacting with the gain setting. The differential signal gain for the circuit of Figure 7-8 is:

Equation 5. AD = 1 + 2 × RF / RG

Because the OPA695 is a current-feedback amplifier, bandwidth is principally controlled with the feedback resistor value: Figure 7-8 shows a typical value of 500 Ω. However, the differential gain can be adjusted with considerable freedom using just the RG resistor. RG can be a reactive network providing an isolated shaping to the differential frequency response. AC-coupled applications often include a blocking capacitor in series with RG. This blocking capacitor reduces the gain to +1 V/V at low frequency, rising to the AD expression shown previously at higher frequencies.

Figure 7-9 shows a differential I/O stage configured as an inverting amplifier. In this case, the gain resistors (RG) become part of the input resistance for the source. This configuration provides a better noise performance than the noninverting configuration, but limits the flexibility in setting the input impedance separately from the gain.

OPA695 Inverting Input Differential I/O AmplifierFigure 7-9 Inverting Input Differential I/O Amplifier

The two noninverting inputs provide an easy common-mode control input, particularly if the source is ac-coupled through either blocking caps or a transformer. In either case, the common-mode input voltages on the two noninverting inputs again have a gain of +1 V/V to the output pins, giving easy common-mode control for single-supply operation. In this configuration, the OPA695 constrains the feedback to the 500-Ω region for best frequency response. With RF fixed, the input resistors can be adjusted to the desired gain, but also change the input impedance. The high-frequency common-mode gain for this circuit from input to output is the same as for the signal gain. Again, if the source includes an undesired common-mode signal, the signal can be rejected at the input using blocking caps (for low-frequency and dc common-mode) or a transformer coupling. The differential signal gain in the circuit of Figure 7-9 is:

Equation 6. AD = RF / RG

Using this configuration suppresses the 2nd-harmonics, leaving only 3rd-harmonic terms as the limit to output SFDR. The higher slew rate of the inverting configuration also extends the full-power bandwidth and the range of low intermodulation distortion over the performance bandwidth available from the circuit of Figure 7-8.