JAJSP64I December   2003  – October 2024 OPA695

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics VS = ±5 V, OPA695ID, OPA695IDBV
    6. 5.6  Electrical Characteristics VS = 5 V, OPA695ID, OPA695IDBV
    7. 5.7  Electrical Characteristics VS = ±5 V, OPA695IDGK
    8. 5.8  Electrical Characteristics VS = 5 V, OPA695IDGK
    9. 5.9  Typical Characteristics: VS = ±5 V, OPA695IDBV, OPA695ID
    10. 5.10 Typical Characteristics: VS = 5 V, OPA695IDBV, OPA695ID
    11. 5.11 Typical Characteristics: VS = ±5 V, OPA695IDGK
    12. 5.12 Typical Characteristics: VS = 5 V, OPA695IDGK
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Wideband Current-Feedback Operation
      2. 6.3.2 Input and ESD Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Operating Suggestions
        1. 7.1.1.1 Setting Resistor Values to Optimize Bandwidth
        2. 7.1.1.2 Output Current and Voltage
        3. 7.1.1.3 Driving Capacitive Loads
        4. 7.1.1.4 Distortion Performance
        5. 7.1.1.5 Noise Performance
        6. 7.1.1.6 Thermal Analysis
      2. 7.1.2 LO Buffer Amplifier
      3. 7.1.3 Wideband Cable Driving Applications
        1. 7.1.3.1 Cable Modem Return Path Driver
        2. 7.1.3.2 Arbitrary Waveform Driver
      4. 7.1.4 Differential I/O Applications
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Saw Filter Buffer
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Design-In Tools
        1. 8.1.1.1 Demonstration Fixtures
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.8 Electrical Characteristics VS = 5 V, OPA695IDGK

at TA = +25°C, G = +8 V/V, VS = 5 V, RF = 348 Ω, and RL = 100 Ω to VS /2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VO = 0.5 VPP G = +1 V/V, RF = 511Ω 1400 MHz
G = +2 V/V, RF = 487Ω 960
G = +8 V/V, RF = 348Ω 395
G = +16 V/V, RF = 162Ω 235
Bandwidth for 0.2-dB gain flatness G = +2, VO = 0.5 VPP, RF = 487 Ω 230 MHz
Peaking at a gain of +1 V/V RF = 511 Ω, VO = 0.5 VPP 1 2 dB
LSBW Large-signal bandwidth G = +8 V/V, VO = 2 VPP 310 MHz
SR Slew rate G = +8 V/V, VO = 2-V step 1700 V/μs
Rise and fall time (10% to 90%) G = +8 V/V VO = 0.5-V step 1 ns
VO = 2-V step 1
Settling time To 0.02%, VO = 2-V step 16 ns
To 0.1%, VO = 2-V step 10 ns
HD2 2nd-order harmonic distortion f = 10 MHz VO = 2 VPP, RL = 100 Ω –62 –58 dBc
VO = 2 VPP, RL = 500 Ω –70 –66
HD3 3rd-order harmonic distortion f = 10 MHz VO = 2 VPP, RL = 100 Ω –66 –64 dBc
VO = 2 VPP, RL = 500 Ω –65 –63
en Input voltage noise f > 1 MHz 1.8 2 nV/√Hz
in+ Noninverting input current noise f > 1 MHz 18 19 pA/√Hz
in- Inverting input current noise f > 1 MHz 22 24 pA/√Hz
DC PERFORMANCE
ZOL Open-loop transimpedance gain VO = VS/2 40 70 kΩ
TA = –40°C to +85°C   36
Input offset voltage VCM = VS/2 ±0.3 ±3 mV
TA = –40°C to +85°C   ±4
Average input offset voltage drift VCM = VS/2,TA = –40°C to +85°C    ±15 μV/°C
Noninverting input bias current VCM = VS/2 ±5 ±40 μA
TA = –40°C to +85°C   ±50
Average noninverting input bias current drift VCM = VS/2, TA = –40°C to +85°C   ±170 nA/°C
Inverting input bias current VCM = VS/2 ±5 ±60 μA
TA = –40°C to +85°C   ±70
Average inverting input bias current drift VCM = VS/2, TA = –40°C to +85°C     ±160 nA/°C
INPUT CHARACTERISTICS
CMIR Common-mode input range (positive)(1) 3.2 3.3 V
TA = –40°C to +85°C 3.1
Common-mode input range (negative)(1) 1.7 1.8
TA = –40°C to +85°C 1.9
CMRR Common-mode rejection ratio VCM = VS/2 51 54 dB
TA = –40°C to +85°C 50
Noninverting input resistance 280 || 1.2 kΩ || pF
Inverting input resistance Open-loop 32 Ω
OUTPUT CHARACTERISTICS
VO Output voltage swing (most positive) No load 4.0 4.2 V
TA = –40°C to +85°C 3.8
RL = 100Ω 3.9 4 V
TA = –40°C to +85°C 3.7
Output voltage swing (least positive) No load 0.8 1 V
TA = –40°C to +85°C 1.2
RL = 100Ω 1 1.1 V
TA = –40°C to +85°C 1.3
IO Output current, sourcing VO = VS/2 70 90 mA
TA = –40°C to +85°C   66
Output current, sinking VO = VS/2 –90 –70 mA
TA = –40°C to +85°C   –66
ZOUT Closed-loop output impedance G = +2 V/V, f = 100 kHz 0.05 Ω
POWER SUPPLY
IQ Quiescent current 10.9 11.4 12 mA
TA = –40°C to +85°C   9.1 12.9
–PSRR Negative power-supply rejection ratio 56 dB
DISABLE (Disabled LOW)
Power-down quiescent current VDIS  = 0 V 95 160 μA
TA = –40°C to +85°C    180
Disable time VIN = ±0.25 VDC 1 μs
Enable time VIN = ±0.25 VDC 25 ns
Off isolation G = +8 V/V, f = 10 MHz 70 dB
Output capacitance in disable 4 pF
Turn-on glitch G = +2 V/V, RL = 150 Ω, VIN = 0 V ±100 mV
Turn-off glitch G = +2 V/V, RL = 150 Ω, VIN = 0 V ±20 mV
Enable voltage 3.3 3.5 V
TA = –40°C to +85°C 3.7
Disable voltage threshold 1.7 1.8 V
TA = –40°C to +85°C 1.5
DIS control pin input bias current 75 130 μA
TA = –40°C to +85°C 149
(1) Tested < 3 dB below minimum specified CMRR at ± CMIR limits.