JAJSHS6E
August 2019 – August 2024
OPA810
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics: 10 V
6.6
Electrical Characteristics: 24 V
6.7
Electrical Characteristics: 5 V
6.8
Typical Characteristics: VS = 10 V
6.9
Typical Characteristics: VS = 24 V
6.10
Typical Characteristics: VS = 5 V
6.11
Typical Characteristics: ±2.375-V to ±12-V Split Supply
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
OPA810 Architecture
7.3.2
ESD Protection
7.4
Device Functional Modes
7.4.1
Split-Supply Operation (±2.375 V to ±13.5 V)
7.4.2
Single-Supply Operation (4.75 V to 27 V)
8
Application and Implementation
8.1
Application Information
8.1.1
Amplifier Gain Configurations
8.1.2
Selection of Feedback Resistors
8.1.3
Noise Analysis and the Effect of Resistor Elements on Total Noise
8.2
Typical Applications
8.2.1
Transimpedance Amplifier
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
8.2.2
High-Z Input Data Acquisition Front-End
8.2.3
Multichannel Sensor Interface
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
Thermal Considerations
8.4.2
Layout Example
9
Device and Documentation Support
9.1
サード・パーティ製品に関する免責事項
9.2
Documentation Support
9.2.1
Related Documentation
9.3
ドキュメントの更新通知を受け取る方法
9.4
サポート・リソース
9.5
Trademarks
9.6
静電気放電に関する注意事項
9.7
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
D|8
DBV|5
DCK|5
サーマルパッド・メカニカル・データ
発注情報
jajshs6e_oa
jajshs6e_pm
8.2.1.3
Application Curves
Figure 8-13
Loop-Gain Magnitude vs Frequency for the Transimpedance Amplifier Circuit of
Figure 8-12
Figure 8-14
Loop-Gain Phase vs Frequency for the Transimpedance Amplifier Circuit of
Figure 8-12