JAJSHS6E August   2019  – August 2024 OPA810

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: 10 V
    6. 6.6  Electrical Characteristics: 24 V
    7. 6.7  Electrical Characteristics: 5 V
    8. 6.8  Typical Characteristics: VS = 10 V
    9. 6.9  Typical Characteristics: VS = 24 V
    10. 6.10 Typical Characteristics: VS = 5 V
    11. 6.11 Typical Characteristics: ±2.375-V to ±12-V Split Supply
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 OPA810 Architecture
      2. 7.3.2 ESD Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±2.375 V to ±13.5 V)
      2. 7.4.2 Single-Supply Operation (4.75 V to 27 V)
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Amplifier Gain Configurations
      2. 8.1.2 Selection of Feedback Resistors
      3. 8.1.3 Noise Analysis and the Effect of Resistor Elements on Total Noise
    2. 8.2 Typical Applications
      1. 8.2.1 Transimpedance Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 High-Z Input Data Acquisition Front-End
      3. 8.2.3 Multichannel Sensor Interface
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • D|8
  • DBV|5
  • DCK|5
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

Achieving optimized performance with a high-frequency amplifier such as the OPA810 requires careful attention to board layout parasitics and external component types. The OPA2810EVM can be used as a reference when designing the circuit board. Recommendations that optimize performance include:

  1. Minimize parasitic capacitance to any ac ground for all signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability—on the noninverting input, this capacitance can react with the source impedance to cause unintentional band-limiting. To reduce unwanted capacitance, open a window around the signal I/O pins in all ground and power planes around those pins. Otherwise, ground and power planes must be unbroken elsewhere on the board.
  2. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency, 0.01-µF decoupling capacitors. At the device pins, do not allow the ground and power plane layout to be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Always decouple the power-supply connections with these capacitors. Use larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, on the supply pins. Place these capacitors somewhat farther from the device and share these capacitors among several devices in the same area of the PCB.
  3. Careful selection and placement of external components preserve the high-frequency performance of the OPA810. Resistors must be a low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high-frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, must also be placed close to the package. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values greater than 10 kΩ, this parasitic capacitance can add a pole or zero close to the GBWP of 70 MHz and subsequently affects circuit operation. Keep resistor values as low as possible and consistent with load driving considerations. Lowering the resistor values keeps the resistor noise terms low, and minimizes the effect of parasitic capacitance, however lower resistor values increase the dynamic power consumption because RF and RG become part of the amplifiers output load network. Transimpedance applications (see the Section 8.2.1 section) can use whatever feedback resistor is required by the application as long as the feedback compensation capacitor is set considering all parasitic capacitance terms on the inverting node.
  4. Connections to other wideband devices on the board can be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS for sufficient phase margin and stability. Low parasitic capacitive loads (< 10 pF) do not always require an RS because the OPA810 is nominally compensated to operate with a 10-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed with increase in signal gain (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary onboard, and a higher impedance environment improves distortion. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA810 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device—this total effective impedance must be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value to obtain sufficient phase margin and stability. This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, the signal attenuates because of the voltage divider formed by the series output into the terminating impedance.
  5. Take care to design the PCB layout for optimized thermal dissipation. For the extreme case of 125°C operating ambient, using the approximate 134.8°C/W for the SOIC package, and an internal power of 24-V supply × 4.7-mA 125°C supply current gives a maximum internal power dissipation of 113 mW. This power gives a 15°C increase from ambient to junction temperature. Load power adds to this value and this dissipation must also be calculated to determine the worst-case safe operating point.
  6. Socketing a high-speed device such as the OPA810 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that can almost make achieving a smooth, stable frequency response impossible. Best results are obtained by soldering the OPA810 onto the board.