JAJSK63A April   2023  – November 2023 OPA814

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics:
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and ESD Protection
      2. 7.3.2 FET-Input Architecture With Wide Gain-Bandwidth Product
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Wideband, High-Input Impedance DAQ Front-End
      2. 8.1.2 Wideband, Transimpedance Design Using the OPA814
    2. 8.2 Typical Application
      1. 8.2.1 High-Input-Impedance, 180-MHz, Digitizer Front-End Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • DBV|5
サーマルパッド・メカニカル・データ
発注情報

8.3 Power Supply Recommendations

The OPA814 is intended to operate on supplies ranging from 6 V to 12.6 V. The OPA814 supports single-supply, split, balanced, and unbalanced bipolar supplies. When operating at supplies less than 8 V, consider the input common-mode range of the amplifier. Under these supply conditions, the common-mode must be biased appropriately for linear operation. Therefore, the limit to lower supply-voltage operation is the usable input voltage range for the JFET-input stage.