SBOS940A May   2019  – March 2020 OPA818

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     High-Speed Optical Front-End
  3. 3 Description
    1.     Photodiode Capacitance vs 3-dB Bandwidth
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = ±5 V
    6. 7.6 Typical Characteristics: VS = ±5 V
    7. 7.7 Typical Characteristics: VS = 6 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and ESD Protection
      2. 8.3.2 Feedback Pin
      3. 8.3.3 Decompensated Architecture With Wide Gain-Bandwidth Product
      4. 8.3.4 Low Input Capacitance
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (+4/–2 V to ±6.5 V)
      2. 8.4.2 Single-Supply Operation (6 V to 13 V)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Wideband, Non-Inverting Operation
      2. 9.1.2 Wideband, Transimpedance Design Using OPA818
    2. 9.2 Typical Applications
      1. 9.2.1 High Bandwidth, 100-kΩ Gain Transimpedance Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Non-Inverting Gain of 2 V/V
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.2 Layout Example

OPA818 SBOS940_OPA818_Recommend-layout.gifFigure 58. Layout Recommendation

When configuring the OPA818 as a transimpedance amplifier additional care must be taken to minimize the inductance between the avalanche photodiode (APD) and the amplifier. Always place the photodiode on the same side of the PCB as the amplifier. Placing the amplifier and the APD on opposite sides of the PCB increases the parasitic effects due to via inductance. APD packaging can be quite large which often requires the APD to be placed further away from the amplifier than ideal. The added distance between the two device results in increased inductance between the APD and op amp feedback network as shown in Equation 1. The added inductance is detrimental to a decompensated amplifier's stability since it isolates the APD capacitance from the noise gain transfer function. The noise gain is given by Equation 1. The added PCB trace inductance between the feedback network increases the denominator in Equation 1 thereby reducing the noise gain and the phase margin. In cases where a leaded APD in a TO can is used inductance should be further minimized by cutting the leads of the TO can as short as possible. Also, edge mounting the photodiode on the PCB should be considered versus through the hole if the application allows.

The layout shown in Figure 59 can be improved by following some of the guidelines shown in Figure 60. The two key rules to follow are:

  • Add an isolation resistor RISO as close as possible to the inverting input of the amplifier. Select the value of RISO to be between 10 Ω and 20 Ω. The resistor dampens the potential resonance caused by the trace inductance and the amplifiers internal capacitance.
  • Close the loop between the feedback elements (RF and CF) and RISO as close to the APD pins as possible. This ensures a more balanced layout and reduces the inductive isolation between the APD and the feedback network.

Equation 1. OPA818 SBOS940_OPA818_Eq-NG-Layout.gif

where

  • ZF is the total impedance of the feedback network
  • ZIN is the total impedance of the input network
OPA818 SBOS940_OPA818_Non-ideal-TIA-layout.gifFigure 59. Non-Ideal TIA Layout
OPA818 SBOS940_OPA818_Improved-TIA-layout.gifFigure 60. Improved TIA Layout