JAJSLI5J January   2011  – March 2021 OPA2835 , OPA835

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparision Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA835
    5. 7.5 Thermal Information: OPA2835
    6. 7.6 Electrical Characteristics: VS = 2.7 V
    7. 7.7 Electrical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 2.7 V
    9. 7.9 Typical Characteristics: VS = 5 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Low-Power Applications and the Effects of Resistor Values on Bandwidth
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.25 V to ±2.75 V)
      2. 8.4.2 Single-Supply Operation (2.5 V to 5.5 V)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Noninverting Amplifier
      2. 9.1.2  Inverting Amplifier
      3. 9.1.3  Instrumentation Amplifier
      4. 9.1.4  Attenuators
      5. 9.1.5  Single-Ended to Differential Amplifier
      6. 9.1.6  Differential to Single-Ended Amplifier
      7. 9.1.7  Differential-to-Differential Amplifier
      8. 9.1.8  Gain Setting With OPA835 RUN Integrated Resistors
      9. 9.1.9  Pulse Application With Single-Supply
      10. 9.1.10 ADC Driver Performance
    2. 9.2 Typical Application
      1. 9.2.1 Audio Frequency Performance
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Filters
        1. 9.2.2.1 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 サポート・リソース
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Electrical Characteristics: VS = 2.7 V

at VS+ = +2.7 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, VIN_CM = mid-supply – 0.5 V. TA = 25°C, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNITTEST LEVEL(1)
AC PERFORMANCE
Small-signal bandwidthVOUT = 100 mVPP, G = 151MHzC
VOUT = 100 mVPP, G = 222.5
VOUT = 100 mVPP, G = 57.2
VOUT = 100 mVPP, G = 103
Gain-bandwidth productVOUT = 100 mVPP, G = 1030MHzC
Large-signal bandwidthVOUT = 1 VPP, G = 124MHzC
Bandwidth for 0.1-dB flatnessVOUT = 1 VPP, G = 24MHzC
Slew rate, riseVOUT = 1 VSTEP, G = 2110V/µsC
Slew rate, fallVOUT = 1 VSTEP, G = 2130V/µsC
Rise timeVOUT = 1 VSTEP, G = 29.5nsC
Fall timeVOUT = 1 VSTEP, G = 29nsC
Settling time to 1%, riseVOUT = 1 VSTEP, G = 235nsC
Settling time to 1%, fallVOUT = 1 VSTEP, G = 230nsC
Settling time to 0.1%, riseVOUT = 1 VSTEP, G = 260nsC
Settling time to 0.1%, fallVOUT = 1 VSTEP, G = 265nsC
Settling time to 0.01%, riseVOUT = 1 VSTEP, G = 2120nsC
Settling time to 0.01%, riseVOUT = 1 VSTEP, G = 290nsC
Overshoot/UndershootVOUT = 1 VSTEP, G = 20.5%/0.2%C
Second-order harmonic distortionf = 10 kHz, VIN_CM = mid-supply – 0.5 V–133dBcC
f = 100 kHz, VIN_CM = mid-supply – 0.5 V–110
f = 1 MHz, VIN_CM = mid-supply – 0.5 V–73
Third-order harmonic distortionf = 10 kHz, VIN_CM = mid-supply – 0.5 V–137dBcC
f = 100 kHz, VIN_CM = mid-supply – 0.5 V–125
f = 1 MHz, VIN_CM = mid-supply – 0.5 V–78
Second-order intermodulation distortionf = 1 MHz, 200-kHz Tone Spacing,
VOUT Envelope = 1 VPP,
VIN_CM = mid-supply – 0.5 V		–75dBcC
Third-order intermodulation distortionf = 1 MHz, 200-kHz Tone Spacing,
VOUT Envelope = 1 VPP,
VIN_CM = mid-supply – 0.5 V		–81dBcC
Input voltage noisef = 100 kHz9.3nV/√ HzC
Voltage noise 1/f corner frequency147HzC
AC PERFORMANCE (continued)
Input current noisef = 1 MHz0.45pA/√ HzC
Current noise 1/f corner frequency14.7kHzC
Overdrive recovery time, over/underOverdrive = 0.5 V140/125nsC
Closed-loop output impedancef = 100 kHz0.028ΩC
Channel-to-channel crosstalk (OPA2835)f = 10 kHz–120dBC
DC PERFORMANCE
Open-loop voltage gain (AOL)100120dBA
Input referred offset voltageTA = 25°C–500±100500µVA
TA = 0°C to 70°C–880880B
TA = –40°C to 85°C–10401040
TA = –40°C to 125°C–18501850
Input offset voltage drift(3)TA = 0°C to 70°C–8.5±1.48.5µV/°CB
TA = –40°C to 85°C–9±1.59
TA = –40°C to 125°C–13.5±2.2513.5
Input bias current(2)TA = 25°C50200400nAA
TA = 0°C to 70°C47410B
TA = –40°C to 85°C45425
TA = –40°C to 125°C45530
Input bias current drift(3)TA = 0°C to 70°C–1.4±0.251.4nA/°CB
TA = –40°C to 85°C–1.05±0.1751.05
TA = –40°C to 125°C–1.1±0.1851.1
Input offset currentTA = 25°C–100±13100nAA
TA = 0°C to 70°C–100±13100B
TA = –40°C to 85°C–100±13100
TA = –40°C to 125°C–100±13100
Input offset current drift(3)TA = 0°C to 70°C–1.230±0.2051.230nA/°CB
TA = –40°C to 85°C–0.940±0.1550.940
TA = –40°C to 125°C–0.940±0.1550.940
INPUT
Common-mode input range lowTA = 25°C, < 3 dB degradation in CMRR limit–0.20VA
TA = –40°C to 125°C, < 3-dB degradation in CMRR limit–0.20VB
Common-mode input range highTA = 25°C, < 3-dB degradation in CMRR limit1.51.6VA
TA = –40°C to 125°C, < 3-dB degradation in CMRR limit1.51.6VB
Common-mode rejection ratio88110dBA
Input impedance common-mode250 || 1.2MΩ || pFC
Input impedance differential mode200 || 1kΩ || pFC
OUTPUT
Output voltage lowTA = 25°C, G = 50.150.2VA
TA = –40°C to 125°C, G = 50.150.2VB
Output voltage highTA = 25°C, G = 52.452.5VA
TA = –40°C to 125°C, G = 52.452.5VB
Output saturation voltage, high/lowTA = 25°C, G = 545/13mVC
Output current driveTA = 25°C±25±35mAA
TA = –40°C to 125°C±20mAB
GAIN-SETTING RESISTORS (OPA835IRUN ONLY)
Resistor FB1 to FB2DC resistance237624002424ΩA
Resistor FB2 to FB3DC resistance178218001818ΩA
Resistor FB3 to FB4DC resistance594600606ΩA
Resistor toleranceDC resistance–1%1%A
Resistor temperature coefficientDC resistance< 10PPMC
POWER SUPPLY
Specified operating voltage2.55.5VB
Quiescent operating current per amplifierTA = 25°C175245340µAA
TA = –40°C to 125°C135345µAB
Power supply rejection (±PSRR)88105dBA
POWER DOWN (PIN MUST BE DRIVEN)
Enable voltage thresholdSpecified on above VS–+ 2.1 V1.42.1VA
Disable voltage thresholdSpecified off below VS–+ 0.7 V0.71.4VA
Power-down pin bias currentPD = 0.5 V20500nAA
Power-down quiescent currentPD = 0.5 V0.51.5µAA
Turnon time delayTime from PD = high to VOUT = 90% of final value250nsC
Turnoff time delayTime from PD = low to VOUT = 10% of original value50nsC
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) Current is considered positive out of the pin.
(3) Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range.