JAJSLI5J January   2011  – March 2021 OPA2835 , OPA835

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparision Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA835
    5. 7.5 Thermal Information: OPA2835
    6. 7.6 Electrical Characteristics: VS = 2.7 V
    7. 7.7 Electrical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 2.7 V
    9. 7.9 Typical Characteristics: VS = 5 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Low-Power Applications and the Effects of Resistor Values on Bandwidth
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.25 V to ±2.75 V)
      2. 8.4.2 Single-Supply Operation (2.5 V to 5.5 V)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Noninverting Amplifier
      2. 9.1.2  Inverting Amplifier
      3. 9.1.3  Instrumentation Amplifier
      4. 9.1.4  Attenuators
      5. 9.1.5  Single-Ended to Differential Amplifier
      6. 9.1.6  Differential to Single-Ended Amplifier
      7. 9.1.7  Differential-to-Differential Amplifier
      8. 9.1.8  Gain Setting With OPA835 RUN Integrated Resistors
      9. 9.1.9  Pulse Application With Single-Supply
      10. 9.1.10 ADC Driver Performance
    2. 9.2 Typical Application
      1. 9.2.1 Audio Frequency Performance
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Filters
        1. 9.2.2.1 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 サポート・リソース
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1.8 Gain Setting With OPA835 RUN Integrated Resistors

The OPA835 RUN package option includes integrated gain-setting resistors for the smallest possible footprint on a printed circuit board (≈ 2.00 mm x 2.00 mm). By adding circuit traces on the PCB, gains of +1, –1, –1.33, +2, +2.33, -3, +4, –4, +5, –5.33, +6.33, –7, +8 and inverting attenuations of –0.1429, –0.1875, –0.25, –0.33, –0.75 can be achieved.

Figure 9-6 shows a simplified view of how the OPA835IRUN integrated gain-setting network is implemented. Table 9-1 lists the required pin connections for various noninverting and inverting gains (reference Figure 8-1 and Figure 8-2). Table 9-2 lists the required pin connections for various attenuations using the inverting-amplifier architecture (reference Figure 8-2). Due to ESD protection devices being used on all pins, the absolute maximum and minimum input voltage range, VS– – 0.7 V to VS+ + 0.7 V, applies to the gain-setting resistors, and so attenuation of large input voltages will require external resistors to implement.

The gain-setting resistors are laser trimmed to 1% tolerance with nominal values of 2.4 kΩ, 1.8 kΩ, and 600 Ω. The gain-setting resistors have excellent temperature coefficient, and gain tracking is superior to using external gain-setting resistors. The 800-Ω resistor and 1.25-pF capacitor in parallel with the 2.4-kΩ gain-setting resistor provide compensation for best stability and pulse response.

GUID-B2F63D23-37DB-430B-9458-F0ABDC523950-low.gif Figure 9-6 OPA835IRUN Gain-Setting Network
Table 9-1 Gain Settings
NONINVERTING GAIN
(Figure 8-1)		 INVERTING GAIN
(Figure 8-2)		 SHORT PINS SHORT PINS SHORT PINS SHORT PINS
1 V/V (0 dB) — 1 to 9 —
2 V/V (6.02 dB) –1 V/V (0 dB) 1 to 9 2 to 8 6 to GND —
2.33 V/V (7.36 dB) –1.33 V/V (2.5 dB) 1 to 9 2 to 8 7 to GND —
4 V/V (12.04 dB) –3 V/V (9.54 dB) 1 to 8 2 to 7 6 to GND —
5 V/V (13.98 dB) –4 V/V (12.04 dB) 1 to 9 2 to 7 or 8 7 to 8 6 to GND
6.33 V/V (16.03 dB) –5.33 V/V (14.54 dB) 1 to 9 2 to 6 or 8 6 to 8 7 to GND
8 V/V (18.06 dB) –7 V/V (16.90 dB) 1 to 9 2 to 7 6 to GND —
Table 9-2 Attenuator Settings
INVERTING GAIN
(Figure 8-2)		 SHORT PINS SHORT PINS SHORT PINS SHORT PINS
–0.75 V/V (–2.5 dB) 1 to 7 2 to 8 9 to GND —
–0.333 V/V (–9.54 dB) 1 to 6 2 to 7 8 to GND —
–0.25 V/V (–12.04 dB) 1 to 6 2 to 7 or 8 7 to 8 9 to GND
–0.1875 V/V (–14.54 dB) 1 to 7 2 to 6 or 8 6 to 8 9 to GND
–0.1429 V/V (–16.90 dB) 1 to 6 2 to 7 9 to GND —