JAJSLJ2J January   2011  – March 2021 OPA2836 , OPA836

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA836
    5. 7.5 Thermal Information: OPA2836
    6. 7.6 Electrical Characteristics: VS = 2.7 V
    7. 7.7 Electrical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 2.7 V
    9. 7.9 Typical Characteristics: VS = 5 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Low-Power Applications and the Effects of Resistor Values on Bandwidth
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.25 V to ±2.75 V)
      2. 8.4.2 Single-Supply Operation (2.5 V to 5.5 V)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Noninverting Amplifier
      2. 9.1.2  Inverting Amplifier
      3. 9.1.3  Instrumentation Amplifier
      4. 9.1.4  Attenuators
      5. 9.1.5  Single-Ended-to-Differential Amplifier
      6. 9.1.6  Differential-to-Signal-Ended Amplifier
      7. 9.1.7  Differential-to-Differential Amplifier
      8. 9.1.8  Gain Setting With OPA836 RUN Integrated Resistors
      9. 9.1.9  Pulse Application With Single-Supply
      10. 9.1.10 ADC Driver Performance
    2. 9.2 Typical Applications
      1. 9.2.1 Audio Frequency Performance
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Filters
        1. 9.2.2.1 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
    6. 12.6 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1.5 Single-Ended-to-Differential Amplifier

Figure 9-2 shows an amplifier circuit that is used to convert single-ended signals to differential, and provides gain and level shifting. This circuit can be used for converting signals to differential in applications like line drivers for Cat5 cabling or driving differential-input SAR and ΔΣ ADCs.

With VIN = VREF + VSIG , the output of the amplifier may be calculated according to Equation 4.

Equation 4. GUID-A6BCD33F-4419-4A60-868F-A75F9FE82005-low.gif

The differential-signal gain of the circuit is 2 × G, and VREF provides a reference around which the output signal swings. The differential output signal is in-phase with the single-ended input signal.

GUID-471820E0-F13E-404F-A864-072F84692836-low.gif Figure 9-2 Single Ended to Differential Amplifier

Line termination on the output can be accomplished with resistors RO. The differential impedance seen from the line will be 2 × RO. For example, if 100-Ω Cat5 cable is used with double termination, the amplifier is typically set for a differential gain of 2 V/V (6 dB) with RF = 0 Ω (short), RG = open, 2R = 1 kΩ, R1 = 0 Ω, R = 499 Ω to balance the input bias currents, and RO = 49.9 Ω for output line termination. This configuration is shown in Figure 9-3.

For driving a differential-input ADC the situation is similar, but the output resistors, RO are selected with a capacitor across the ADC input for optimum filtering and settling-time performance.

GUID-B418A924-3CED-4103-9880-7F635FC1D6EC-low.gifFigure 9-3 Cat5 Line Driver With Gain = 2 V/V (6 dB)