JAJSLJ2J January   2011  – March 2021 OPA2836 , OPA836

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA836
    5. 7.5 Thermal Information: OPA2836
    6. 7.6 Electrical Characteristics: VS = 2.7 V
    7. 7.7 Electrical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 2.7 V
    9. 7.9 Typical Characteristics: VS = 5 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Low-Power Applications and the Effects of Resistor Values on Bandwidth
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.25 V to ±2.75 V)
      2. 8.4.2 Single-Supply Operation (2.5 V to 5.5 V)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Noninverting Amplifier
      2. 9.1.2  Inverting Amplifier
      3. 9.1.3  Instrumentation Amplifier
      4. 9.1.4  Attenuators
      5. 9.1.5  Single-Ended-to-Differential Amplifier
      6. 9.1.6  Differential-to-Signal-Ended Amplifier
      7. 9.1.7  Differential-to-Differential Amplifier
      8. 9.1.8  Gain Setting With OPA836 RUN Integrated Resistors
      9. 9.1.9  Pulse Application With Single-Supply
      10. 9.1.10 ADC Driver Performance
    2. 9.2 Typical Applications
      1. 9.2.1 Audio Frequency Performance
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Filters
        1. 9.2.2.1 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
    6. 12.6 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 Electrical Characteristics: VS = 5 V

at VS+ = +5 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 1 kΩ, G = 1 V/V, input and output referenced to mid-supply. TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1)
AC PERFORMANCE
Small-signal bandwidth VOUT = 100 mVPP, G = 1 205 MHz C
VOUT = 100 mVPP, G = 2 100
VOUT = 100 mVPP, G = 5 28
VOUT = 100 mVPP, G = 10 11.8
Gain-bandwidth product VOUT = 100 mVPP, G = 10 118 MHz C
Large-signal bandwidth VOUT = 2 VPP, G = 2 87 MHz C
Bandwidth for 0.1-dB flatness VOUT = 2 VPP, G = 2 29 MHz C
Slew rate, rise VOUT = 2-V Step, G = 2 560 V/µs C
Slew rate, fall VOUT = 2-V Step, G = 2 580 V/µs C
Rise time VOUT = 2-V Step, G = 2 3 ns C
Fall time VOUT = 2-V Step, G = 2 3 ns C
AC PERFORMANCE (continued)
Settling time to 1%, rise VOUT = 2-V Step, G = 2 22 ns C
Settling time to 1%, fall VOUT = 2-V Step, G = 2 22 ns C
Settling time to 0.1%, rise VOUT = 2-V Step, G = 2 30 ns C
Settling time to 0.1%, fall VOUT = 2-V Step, G = 2 30 ns C
Settling time to 0.01%, rise VOUT = 2-V Step, G = 2 40 ns C
Settling time to 0.01%, fall VOUT = 2-V Step, G = 2 45 ns C
Overshoot/Undershoot VOUT = 2-V Step, G = 2 7.5%/5% C
Second-order harmonic distortion f = 10 kHz –133 dBc C
f = 100 kHz –120
f = 1 MHz –85
Third-order harmonic distortion f = 10 kHz –140 dBc C
f = 100 kHz –130
f = 1 MHz –105
Second-order intermodulation distortion f = 1 MHz, 200 kHz Tone Spacing,
VOUT Envelope = 2 VPP		 –79 dBc C
Third-order intermodulation distortion f = 1 MHz, 200 kHz Tone Spacing,
VOUT Envelope = 2 VPP		 –91 dBc C
Signal-to-noise ratio, SNR f = 1 kHz, VOUT = 1 VRMS,
22 kHz bandwidth		 0.00013% C
–117.6 dBc
Total harmonic distortion, THD f = 1 kHz, VOUT = 1 VRMS 0.00003% C
–130 dBc
Input voltage noise f = 100 KHz 4.6 nV/√ Hz C
Voltage noise 1/f corner frequency 215 Hz C
Input current noise f > 1 MHz 0.75 pA/√ Hz C
Current noise 1/f corner frequency 31.7 kHz C
Overdrive recovery time, over/under Overdrive = 0.5 V 55/60 ns C
Closed-loop output impedance f = 100 kHz 0.02 Ω C
Channel to channel crosstalk (OPA2836) f = 10 kHz –120 dB C
DC PERFORMANCE
Open-loop voltage gain (AOL) 100 122 dB A
Input referred offset voltage TA = 25°C –400 ±65 400 µV A
TA = 0°C to 70°C –685 685 B
TA = –40°C to 85°C –765 765
TA = –40°C to 125°C –1080 1080
Input offset voltage drift(2) TA = 0°C to 70°C –6.3 ±1.05 6.3 µV/°C B
TA = –40°C to 85°C –6.1 ±1 6.1
TA = –40°C to 125°C –6.8 ±1.1 6.8
Input bias current(3) TA = 25°C 300 650 1000 nA A
TA = 0°C to 70°C 190 1400 B
TA = –40°C to 85°C 120 1550
TA = –40°C to 125°C 120 1850
Input bias current drift(2) TA = 0°C to 70°C ±0.34 ±2 nA/°C B
TA = –40°C to 85°C ±0.34 ±2
TA = –40°C to 125°C ±0.38 ±2.3
DC PERFORMANCE (continued)
Input offset current TA = 25°C ±30 ±180 nA A
TA = 0°C to 70°C ±30 ±200 B
TA = –40°C to 85°C ±30 ±215
TA = –40°C to 125°C ±30 ±250
Input offset current drift(2) TA = 0°C to 70°C ±80 ±480 pA/°C B
TA = –40°C to 85°C ±100 ±600
TA = –40°C to 125°C ±110 ±660
INPUT
Common-mode input range low TA = 25°C,
< 3-dB degradation in CMRR limit		 –0.2 0 V A
TA = –40°C to 125°C,
< 3-dB degradation in CMRR limit		 –0.2 0 V B
Common-mode input range high TA = 25°C,
< 3-dB degradation in CMRR limit		 3.8 3.9 V A
TA = –40°C to 125°C,
< 3-dB degradation in CMRR limit		 3.8 3.9 V B
Input linear operating voltage range TA = 25°C,
< 6-dB degradation in THD		 –0.3 to 4.05 V C
Common-mode rejection ratio 94 116 dB A
Input impedance common mode 100 || 1.2 MΩ || pF C
Input impedance differential mode 100 || 1 kΩ || pF C
OUTPUT
Output voltage low TA = 25°C, G = 5 0.15 0.2 V A
TA = –40°C to 125°C, G = 5 0.15 0.2 V B
Output voltage high TA = 25°C, G = 5 4.75 4.8 V A
TA = –40°C to 125°C, G = 5 4.75 4.8 V B
Output saturation voltage, high/low TA = 25°C, G = 5 100/50 mV C
Output current drive TA = 25°C ±40 ±50 mA A
TA = –40°C to 125°C ±40 ±50 mA B
GAIN SETTING RESISTORS (OPA836IRUN ONLY)
Resistor FB1 to FB2 DC resistance 1584 1600 1616 Ω A
Resistor FB2 to FB3 DC resistance 1188 1200 1212 Ω A
Resistor FB3 to FB4 DC resistance 396 400 404 Ω A
Resistor tolerance DC resistance –1 1% A
Resistor temperature coefficient DC resistance <10 PPM C
POWER SUPPLY
Specified operating voltage 2.5 5.5 V B
Quiescent operating current per amplifier TA = 25°C 0.8 1.0 1.2 mA A
TA = –40°C to 125°C 0.65 1.5 mA B
Power supply rejection (±PSRR) 94 108 dB A
POWER DOWN
Enable voltage threshold Specified "on" above VS–+ 2.1 V 2.1 V A
Disable voltage threshold Specified "off" below VS–+ 0.7 V 0.7 V A
Power-down pin bias current PD = 0.5 V 20 500 nA A
Power-down quiescent current PD = 0.5 V 0.5 1.5 µA A
Turnon time delay Time from PD = high to VOUT = 90% of final value 170 ns C
Turnoff time delay Time from PD = low to VOUT = 10% of original value 35 ns C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range.
(3) Current is considered positive out of the pin.