JAJSDO2D August   2017  – September 2024 OPA838

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics VS = 5 V
    6. 6.6 Electrical Characteristics VS = 3 V
    7. 6.7 Typical Characteristics: VS = 5 V
    8. 6.8 Typical Characteristics: VS = 3 V
    9. 6.9 Typical Characteristics: Over Supply Range
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Common-Mode Voltage Range
      2. 7.3.2 Output Voltage Range
      3. 7.3.3 Power-Down Operation
      4. 7.3.4 Trade-Offs in Selecting The Feedback Resistor Value
      5. 7.3.5 Driving Capacitive Loads
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 7.4.2 Single-Supply Operation (2.7 V to 5.4 V)
      3. 7.4.3 Power Shutdown Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Noninverting Amplifier
      2. 8.1.2 Inverting Amplifier
      3. 8.1.3 Output DC Error Calculations
      4. 8.1.4 Output Noise Calculations
    2. 8.2 Typical Applications
      1. 8.2.1 High-Gain Differential I/O Designs
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transimpedance Amplifier
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 開発サポート
        1. 9.1.1.1 TINA-TI™シミュレーション ソフトウェア (無償ダウンロード)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics VS = 3 V

at VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, and TA ≈ 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1)
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 20 mVPP, G = 6 (peaking < 4 dB) 70 86 MHz C
VOUT = 20 mVPP, G = 10, RF = 1.6 kΩ 50 C
VOUT = 20 mVPP, G = 100, RF = 16.9 kΩ 3 C
GBP Gain-bandwidth product VOUT = 20 mVPP, G = 100 240 300 MHz C
LSBW Large-signal bandwidth VOUT = 2 VPP, G = 6 45 MHz C
Bandwidth for 0.1-dB flatness VOUT = 200 mVPP, G = 6 9 MHz C
SR Slew rate From LSBW(2) 250 350 V/µs C
Overshoot, undershoot VOUT = 1-V step, G = 6, input tR = 6 ns 2% 4% C
tR, tF Rise, fall time VOUT = 1-V step, G = 6, input tR = 6 ns 6.3 7 ns C
Settling time to 0.1% VOUT = 1-V step, G = 6, input tR = 6 ns 30 ns C
Settling time to 0.01% VOUT = 1-V step, G = 6, input tR = 6 ns 40 ns C
HD2 Second-order harmonic distortion f = 100 kHz, VO = 2 VPP, G = 6 (see Figure 8-1) –108 dBc C
HD3 Third-order harmonic distortion f = 100 kHz, VO = 2 VPP, G = 6 (see Figure 8-1) –125 dBc C
Input voltage noise f > 1 kHz 1.8 nV/√Hz C
Voltage noise 1/f corner frequency 100 Hz C
Input current noise f > 100 kHz 1.0 pA/√Hz C
Current noise 1/f corner frequency 7 kHz C
Overdrive recovery time G = 6, 2 x output overdrive, dc-coupled 50 ns C
Closed-loop output impedance f = 1 MHz, G = 6 0.3 Ω C
DC PERFORMANCE
AOL Open-loop voltage gain VO = ±1 V, RL = 2 kΩ 110 125 dB A
Input-referred offset voltage TA ≈ 25°C (DXB package) –150 ±15 150 µV A
TA ≈ 25°C –125 ±15 125 A
TA = 0°C to 70°C –165 ±15 200 B
TA = –40°C to +85°C –230 ±15 220 B
TA = –40°C to +125°C –230 ±15 285 B
Input offset voltage drift(5) TA = –40°C to +125°C (4) –1.6 ±0.4 1.6 µV/°C B
Input bias current(3) TA ≈ 25°C 0.7 1.5 2.8 µA A
TA = 0°C to 70°C 0.2 1.5 3.5 B
TA = –40°C to +85°C 0.2 1.5 3.7 B
TA = –40°C to +125°C 0.2 1.5 4.4 B
Input bias current drift(5) TA = –40°C to +125°C 4.5 7.8 17 nA/°C B
Input offset current TA ≈ 25°C (DXB package) –100 ±20 100 nA A
TA ≈ 25°C –70 ±20 70 A
TA = 0°C to 70°C –83 ±20 93 B
TA = –40°C to +85°C –105 ±20 100 B
TA = –40°C to +125°C –105 ±13 120 B
Input offset current drift(5) TA = –40°C to +125°C –500 ±20 500 pA/°C B
INPUT
Common-mode input range, low TA ≈ 25°C, CMRR > 92 dB VS– – 0.2 VS– – 0 V A
TA = –40°C to 125°C, CMRR > 92 dB VS– – 0 V B
Common-mode input range, high TA ≈ 25°C, CMRR > 92 dB VS+ – 1.3 VS+ – 1.2 V A
TA = –40°C to +125°C, CMRR > 92 dB VS+ – 1.3 V B
CMRR Common-mode rejection ratio 95 105 dB A
Input impedance common-mode 55 || 1.1 MΩ || pF C
Input impedance differential mode 30 || 1.3 kΩ || pF C
OUTPUT
VOL Output voltage, low TA ≈ 25°C, G = 6 VS– + 0.05 VS– + 0.1 V A
TA = –40°C to +125°C, G = 6 VS– + 0.1 VS– + 0.2 B
VOH Output voltage, high TA ≈ 25°C, G = 6 VS+ – 0.1 VS+ – 0.05 V A
TA = –40°C to +125°C, G = 6 VS+ – 0.2 VS+ – 0.1 B
Maximum current into a resistive load TA ≈ 25°C, ±0.77 V into 26.7 Ω, VIO < 2 mV ±28 ±30 mA A
Linear current into a resistive load TA ≈ 25°C, ±0.88 V into 37 Ω, AOL > 70 dB ±23 ±25 mA A
TA = –40°C to +125°C, ±0.76 V into 37 Ω,
AOL > 70 dB		 ±20 ±23 B
DC output impedance G = 6 0.02 Ω C
POWER SUPPLY
Specified operating voltage 2.7 5 5.4 V B
Quiescent operating current TA ≈ 25°C (DXB package)(6) 875 930 970 µA A
TA ≈ 25°C(6) 890 930 970 A
TA = –40°C to +125°C 680 930 1350 B
dIq/dT Quiescent current temperature coefficient TA = –40°C to +125°C 2.2 2.7 3.2 µA/°C B
+PSRR Positive power-supply rejection ratio 95 110 dB A
–PSRR Negative power-supply rejection ratio 90 105 dB A
POWER DOWN (Pin Must be Driven, SOT23-6 and SC70-6)
Enable voltage threshold Specified on above VS– + 1.5 V 1.5 V A
Disable voltage threshold Specified off  below VS– + 0.55 V 0.55 V A
Disable pin bias current PD = VS– to VS+ –50 20 50 nA A
Power-down quiescent current PD = 0.55 V 0.1 1 µA A
Turn-on time delay Time from PD = high to VOUT = 90% of final value 3.5 µs C
Turn-off time delay Time from PD = low to VOUT = 10% of original value 100 ns C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (0.8 × VPEAK / √2) × 2π × f–3dB where this f–3dB is the typical measured 4-VPP bandwidth at gains of 6 V/V.
(3) Current is considered positive out of the pin.
(4) Input offset voltage drift, input bias current drift, and input offset current drift typical specifications are mean ± 1σ characterized by the full temperature range end-point data. Maximum drift specifications are set by the min, max packaged test range on the wafer-level screened drift. Drift is not specified by the final automated test equipment (ATE) or by QA sample testing.
(5) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range.
(6) The typical specification is at 25°C TJ. The minimum and maximum limits are expanded for the ATE to account for an ambient range from 22°C to 32°C with a 4-µA/°C temperature coefficient on the supply current.