The OPA857 is a wideband, fast overdrive recovery, fast-settling, ultralow-noise transimpedance amplifier targeted at photodiode monitoring applications. With selectable feedback resistance, the OPA857 simplifies the design of high-performance optical systems. Very fast overload recovery time and internal input protection provide the best combination to protect the remainder of the signal chain from overdrive while minimizing recovery time. The two selectable transimpedance gain configurations allow high dynamic range and flexibility required in modern transimpedance amplifier applications. The OPA857 is available in a 3-mm × 3-mm VQFN package.
The device is characterized for operation over the full industrial temperature range from –40°C to +85°C.
DEVICE NAME | PACKAGE | BODY SIZE |
---|---|---|
OPA857 | VQFN (16) | 3 mm × 3 mm |
Changes from C Revision (April 2014) to D Revision
Changes from B Revision (January 2014) to C Revision
Changes from A Revision (December 2013) to B Revision
Changes from * Revision (December 2013) to A Revision
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | Supply voltage, VS– to VS+ | 3.8 | V | |
Input and output voltage, VIN, VOUT pins | (VS–) – 0.7 | (VS+) + 0.7 | ||
Differential input voltage | 1 | |||
Current | Output current | 50 | mA | |
Input current, VIN pin | 10 | |||
Continuous power dissipation | See Thermal Information table | |||
Temperature | Maximum junction, TJ | 150 | °C | |
Maximum junction, TJ (continuous operation, long-term reliability) | 140 | |||
Operating free-air, TA | –40 | 85 | ||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VSS | Supply input voltage | 2.7 | 3.3 | 3.6 | V |
TJ | Operating junction temperature | –40 | 85 | °C |
THERMAL METRIC(1) | OPA857 | UNIT | |
---|---|---|---|
RGT (VQFN) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 67.1 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 91.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 41.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 7.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 41.7 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | 23.1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | TEST LEVEL(1) | |
---|---|---|---|---|---|---|---|
AC PERFORMANCE | |||||||
Small-signal bandwidth | CTRL = 1, TA = –40°C to +85°C | 105 | MHz | C | |||
CTRL = 0, TA = –40°C to +85°C | 125 | MHz | C | ||||
SR | Slew rate (differential) | VOUT = 1-V step | 215 | V/μs | C | ||
tS | Settling time to 1% | VOUT = 0.5-V step, CTRL = 0, TA = 25°C | 8 | ns | B | ||
VOUT = 0.5-V step, CTRL = 1, TA = 25°C | 8 | ns | B | ||||
Settling time to 0.001% | VOUT = 0.5-V step, CTRL = 0 | 600 | ns | C | |||
VOUT = 0.5-V step, CTRL = 1 | 700 | ns | C | ||||
HD2 | Second-harmonic distortion | VOUT = 0.5 VPP, f = 10 MHz, RF = 5 kΩ, TA = 25°C | –80 | dBc | C | ||
VOUT = 0.5 VPP, f = 10 MHz, RF = 20 kΩ, TA = 25°C | –83 | dBc | C | ||||
HD3 | Third-harmonic distortion | VOUT = 0.5 VPP, f = 10 MHz, RF = 5 kΩ, TA = 25°C | –88 | dBc | C | ||
VOUT = 0.5 VPP, f = 10 MHz, RF = 20 kΩ, TA = 25°C | –83 | dBc | C | ||||
Equivalent input-referred current noise | CTRL = 0, using 135-MHz brickwall filter | 25 | nARMS | C | |||
CTRL = 1, using 135-MHz brickwall filter | 15 | nARMS | C | ||||
Overdrive recovery time | IIN = 2x overload, CTRL = 1, settling to 1% of final value | 25 | ns | B | |||
Closed-loop output impedance | f = 1 MHz (differential) | 50 | Ω | C | |||
DC PERFORMANCE | |||||||
Transimpedance gain | CTRL = 1 into 500 Ω(4)(5) | 18.2 | kΩ | C | |||
CTRL = 0 into 500 Ω(4)(5) | 4.5 | kΩ | C | ||||
Transimpedance gain error | TA = 25°C, RF = 20 kΩ and RF = 5 kΩ | ±1% | ±15% | A | |||
VOO | Output offset voltage | TA = +25°C | ±1 | ±5 | mV | A | |
TA = –40°C to +85°C(3) | ±6 | mV | B | ||||
Output offset voltage drift | TA = –40°C to +85°C(3) | ±15 | μV/°C | C | |||
VICR | Common-mode voltage range | TA = 25°C, OUTN | 1.78 | 1.83 | 1.88 | V | A |
INPUT | |||||||
Input pin capacitance | 2 | pF | C | ||||
OUTPUT | |||||||
Output voltage swing | OUT, TA = 25°C | 0.6 | 1.9 | V | A | ||
TA = –40°C to +85°C(3) | 1.9 | V | B | ||||
Output current drive (for linear operation) |
OUT, differential 50-Ω between OUT and OUTN | +5 | mA | C | |||
–20 | mA | C | |||||
POWER SUPPLY | |||||||
Quiescent operating current | CTRL = 0, TA = 25°C | 20.5 | 23.4 | 26.3 | mA | A | |
CTRL = 0, TA = –40°C to +85°C(3) | 20.0 | 26.8 | mA | B | |||
CTRL = 1, TA = 25°C | 20.5 | 23.4 | 26.3 | mA | A | ||
CTRL = 1, TA = –40°C to +85°C(3) | 20.0 | 26.8 | mA | B | |||
PSRR | Power-supply rejection ratio | At dc, TA = 25°C | 70 | 80 | dB | A | |
f = 10 MHz, TA = –40°C to +85°C(3) | 15 | 18 | dB | B | |||
LOGIC LEVEL (CTRL) | |||||||
VIH | High-level input voltage | 2 | V | A | |||
VIL | Low-level input voltage | 0.8 | V | A | |||
High-level control pin input bias current | 1 | µA | A | ||||
Low-level control pin input bias current | 1 | µA | A |
TZ Gain = 20 kΩ, TA = 25°C, RLOAD = 500 Ω, f = 50 MHz |
The OPA857 provides a unique combination of low-noise, high-bandwidth, and high-transimpedance gain. The amplifier is optimized to achieve greater than 100-MHz bandwidth on either the 5-kΩ or 20-kΩ transimpedance gain for the lowest possible RMS noise on the output for a targeted low input capacitance of
1.5 pF. Note that this 1.5-pF capacitance includes the board parasitic; thus, great attention must be placed on minimizing stray capacitance in the layout. This value is selected because the device is expected to be driven by a photodiode with biasing high enough to include the photodiode capacitance contribution between approximately 0.5 pF and 0.7 pF, leaving between 0.8 pF to 1 pF for the external parasitic.
The OPA857 is a dedicated transimpedance amplifier with a pseudo-differential output. A block diagram is provided in the Functional Block Diagram section.
There are four distinct blocks in this diagram: a transimpedance amplifier (TIA), a reference voltage (REF), a test structure (TEST), and an internal clamping circuit (CLAMP).
The TIA block of the Functional Block Diagram includes two selectable gain configurations: RF1 and RF2. For a 500-Ω load, including the GND alternatives resulting from the internal 25-Ω series resistor on each output, the resulting gain is 4.5 kΩ or 18.2 kΩ. The TIA block is designed to provide excellent bandwidth (> 100 MHz) in both gain configurations with the lowest possible RMS noise over the entire bandwidth. This level of performance is achieved by minimizing the noise gain peaking at higher frequencies. The noise gain peaking resulting from feedback and source capacitance is the main noise contributor in high-speed transimpedance amplifiers.
The reference voltage block of the Functional Block Diagram has several purposes: this block provides an adequate dc reference voltage to the input, and provides a dc reference at the output (thus allowing the dc-coupled solution to interface to a fully-differential signal chain). The CMRR provided by the fully-differential signal chain reduces any feedthrough from the OPA857 power supply, thereby increasing the PSRR of the amplifier.
The test structure block is available on the pinout, but the main purpose of this structure is to allow the device characterization to proceed as smoothly as possible.
The internal clamping circuit block and ESD diodes on the IN pin are used for internal protection and to make sure that the amplifier can recover quickly after saturation.
These blocks are each described in further detail in the Feature Description section.
The amplifier of the TIA block has a class-A output stage, which limits its usable swing from the common-mode voltage of 1.83 V to the negative rail. Because the internal protection allows excellent overdrive recovery, the negative swing cannot go closer than 0.6 V to the rail. The resulting output dynamic range of the OPA857 on a 3.3-V supply is 1.2 V. This 1.2-V swing corresponds to a maximum input current of 60 µA in the high-gain configuration, and 240 µA in the low-gain configuration. A 25-Ω series resistor between the internal output of the TIA block and OUT (pin 8) limits the amplifier load during short-circuit conditions. A similar 25-Ω series resistor also exists between the output of the reference voltage amplifier and OUTN (pin 5). The internal resistors on OUT and OUTN reduce the overall gain of the OPA857. With a 500-Ω differential load, the attenuation resulting from the load is 0.83 dB, which affects the overall transimpedance gain. Because of the load attenuation, the 20-kΩ transimpedance gain is reduced to an effective 18.2 kΩ, while the 5-kΩ internal resistor gain is reduced to an effective 4.5-kΩ internal resistor.
The reference output voltage is set to be 5/9th of the power supply. Thus, for a single 3.3-V supply, the reference voltage is 1.83 V. A wideband amplifier with low output impedance to high frequencies is used in the reference voltage block. The amplifier output drives two paths: the first path drives the output (OUTN) through a 25-Ω series resistor, while the second path drives the noninverting input of the TIA block. The output from the second path is filtered through an RC filter in order to reduce the noise contribution from the reference block.
In order to evaluate the low input capacitance condition on the input of the OPA857, simply evaluate the OPA857 performance without the photodiode. An integrated voltage-to-current conversion is implemented and can be accessed with the use of Test_SD (pin 13) and Test_IN (pin 14). This V-to-I converter structure is represented in Figure 37. If required, a capacitor can be added to IN (pin 15) to match the target input capacitance during normal operation with an external photodiode. The test structure in Figure 37 allows for the evaluation of the OPA857 as a TIA using standard lab equipment, such as function generators and network analyzers.
When using a photodiode, make sure that this source is turned off completely. This test structure is not intended to be used as a output dc-control voltage.
The OPA857 is built using a very high-speed, complementary, BICMOS process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 38.
These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30-mA continuous current. Use additional external low-capacitance protection where higher currents are possible.
The device transimpedance gain is controlled with the CTRL pin. Setting the CTRL pin high results in selecting the high-gain configuration. Setting the CTRL pin low results in selecting the low-gain configuration, as described in Table 1.
The OPA857 operates in normal mode when the input is driven by a photodiode. In test mode, the test structure described in the Integrated Test Structure (TEST) Block section is used to emulate a photodiode using a voltage input. Table 2 describes how to configure the OPA857 in each mode.
MODE | Test_IN PIN CONNECTED TO | Test_SD PIN CONNECTED TO |
---|---|---|
Normal mode | +VS | GND |
Test mode | AC-coupled input using a series cap or dc-coupled signal on a 2.1-V (approx) offset voltage |
+VS |
Set an adequate dc voltage at the input to make sure that the output is operating within normal operation. At minimum, the output of the TIA block must be set to 5/9th of the supply voltage in preparation for a pulse configuration. For sine-wave operation, as required when measuring a frequency response, set the dc voltage on the OUT pin to allow the full sine-wave amplitude and avoid clipping. In such a case, the OUT pin voltage is set lower than 5/9th of the supply voltage.
Note that the 2-kΩ internal resistance used for the V-to-I conversion is not trimmed and can vary ±15% with process. Therefore, the source must be capable of sourcing both dc and ac voltages to make sure that the output voltage swing is compliant with the class-A output stage of the TIA block. Any change in the test circuit configuration (such as gain change) requires a new calibration of the internal V-to-I converter.
Again if a photodiode is used, the internal V-to-I converter must be shut off completely. Failure to do so results in degraded performance and higher than normal quiescent current.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The OPA857 is a transimpedance amplifier offering two selectable gains. This device is used in conjunction with a photodiode at its input. The output is pseudo differential and may or may not require the use of a fully differential amplifier, depending on the analog-to-digital converter (ADC) used for implementation.
The OPA857 requires a photodiode to be connected to the positive bias voltage because the output voltage can only swing down from the reference voltage (1.85 V for a 3.3-V supply) to ground.
Figure 39 presents a complete end-to-end receive signal chain for an optical input. It includes a high-speed photodiode, the OPA857, a THS4541 fully-differential amplifier, and a 16-bit, 160-MSPS, high-speed ADC. For the complete wide-bandwidth, optical front-end reference design, go to http://www.ti.com/tool/TIDA-00725.
For this example, use the values listed in Table 3 for the input parameters.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Supply voltage | 5-V external supply |
Analog bandwidth | 120 MHz |
ADC sampling rate | 160 MSPS |
Maximum system gain | 100 kΩ |
Programmable transimpedance gain | 5 kΩ / 20 kΩ |
Maximum signal swing | 1 VPP |
Noise performance | ≥ 60-dB SNR |
Averaged noise performance | < 10-µVRMS |
TZ Gain = 20 kΩ |
TZ Gain = 5 kΩ |
TZ Gain = 20 kΩ |
TZ Gain = 5 kΩ |
At the core of the OPA857 is an ultrawide bandwidth op amp. One of the highlights of the OPA857 is the relatively small change in the transimpedance bandwidth as a function of the internal gain selected; 130 MHz (gain = 5 kΩ) and 105 MHz (gain = 20 kΩ). Theoretically, for a four times increase in gain, the bandwidth should reduce by two times; however, as observed in the case of the OPA857, the results do not follow theory. For more information on the various factors that contribute to an amplifier frequency-response performance when configured as a TIA, see What You Need To Know About Transimpedance Amplifiers – Part 1 on the TI E2E Community website at e2e.ti.com. This blog also contains a reference to an excel calculator to simplify TIA designs when using discrete opamps. The OPA857 is unique in displaying this type of behavior because the CTRL logic controls an internal switch in the amplifier core that recompensates the amplifier open-loop gain characteristic depending upon the logic level. In this application, it it shown how the closed-loop transimpedance bandwidth can be increased to greater than 250 MHz. The circuit used for this test is shown in Figure 44. An external feedback resistor, RF, is added in parallel to the internal transimpedance gain resistors of the OPA857. This resistor has the effect of reducing the overall transimpedance gain, but with increased bandwidth.
For this example, use the values listed in Table 4 for the input parameters.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Supply voltage | 3.3 V |
Output swing | 500 mVPP |
Differential output load | 500 kΩ and 1 kΩ |
Target bandwidth | 250 MHz |
Effective transimpedance gain | 5 kΩ |
Figure 45 shows the frequency response with a feedback resistance of 6.8 kΩ and an output load of 500 Ω. The large amount of peaking indicates a low phase-margin and potential instability. Next, a 0.1-pF feedback capacitor, CF, is added in parallel to the 6.8-kΩ RF. Both RF and CF interact to create pole in the noise gain curve that counteracts the effect of the zero caused by RF, and the total input capacitance at pin IN of the OPA857. The input capacitance is caused by the opamps inherent input capacitance, the photodiode capacitance, and the parasitic input capacitance from the PCB. The pole zero cancellation increases the phase margin, as is evident in the reduced peaking shown in Figure 46. In Figure 47, an output load of 1 kΩ was used, along with an RF = 6.8 kΩ and CF = 0.1 pF. The reduced load helps to increase the op amp open-loop gain, which in turn increases the closed-loop bandwidth of the OPA857 circuit.
RF = 6.8 kΩ |
RF = 6.8 kΩ, CF = 0.1 pF |
RF = 6.8 kΩ, CF = 0.1 pF |