JAJSS86B November   2023  – July 2024 OPA2891 , OPA891

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information - OPA891
    5. 5.5 Thermal Information - OPA2891
    6. 5.6 Electrical Characteristics - RL = 150Ω
    7. 5.7 Electrical Characteristics - RL = 1kΩ
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 Low-Pass Filter Configurations
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selection of Multiplexer
        2. 7.2.2.2 Signal Source
        3. 7.2.2.3 Driving Amplifier
        4. 7.2.2.4 Driving Amplifier Bandwidth Restriction
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 General PowerPAD™ Integrated Circuit Package Design Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • DGN|8
サーマルパッド・メカニカル・データ
発注情報

7.2.2.4 Driving Amplifier Bandwidth Restriction

Restricting excess bandwidth use by including a passive RC filter before the ADC results in better SNR and THD. However, restricting the bandwidth too much results in a excessive operational amplifier settling time. If the amplifier output does not settle quick enough, some residual charges from the previous channel remain in the next sampling interval and appear as crosstalk. One approach to solve this settling issue is to reduce the throughput of the ADC. However, the high sample rate ADC is often selected to meet the need to acquire higher frequency signals, limiting the freedom to reduce the ADC throughput. Due to these tradeoffs, the choice of the filter capacitor becomes critical. Figure 7-6 and Figure 7-7 show SNR and crosstalk as a function of the filter capacitor.

Figure 7-8 shows input settling behavior with three different filter capacitor values. The value of the capacitor changes to filter bandwidth. As the filter bandwidth increases, the settling time improves as shown in Equation 4.

Equation 4. F i l t e r   B a n d w i d t h   ≅ 1 2 π R 1 C 1