JAJSLE9A March   2023  – April 2024 OPA928

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics: 4.5V ≤ VS < 8V
    6. 5.6 Electrical Characteristics: 8V ≤ VS ≤ 16V
    7. 5.7 Electrical Characteristics: 16V < VS ≤ 36V
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Guard Buffer
      2. 6.3.2 Input Protection
      3. 6.3.3 Thermal Protection
      4. 6.3.4 Capacitive Load and Stability
      5. 6.3.5 EMI Rejection
      6. 6.3.6 Common-Mode Voltage Range
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Contamination Considerations
      2. 7.1.2 Guarding Considerations
      3. 7.1.3 Single-Supply Considerations
      4. 7.1.4 Humidity Considerations
      5. 7.1.5 Dielectric Relaxation
      6. 7.1.6 Shielding
    2. 7.2 Typical Applications
      1. 7.2.1 High-Impedance Amplifier
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Transimpedance Amplifier
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Input Bias
          2. 7.2.2.2.2 Offset Voltage
          3. 7.2.2.2.3 Stability
          4. 7.2.2.2.4 Noise
      3. 7.2.3 Improved Diode Limiter
      4. 7.2.4 Instrumentation Amplifier
    3. 7.3 Power-Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
        3. 8.1.1.3 TI のリファレンス・デザイン
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Guard Buffer

To achieve a femtoampere-level input bias current, the OPA928 uses an internal, high-precision, rail-to-rail guard buffer connected to the noninverting input. The guard buffer follows the voltage at the input of the OPA928 to generate a near zero differential voltage across the internal antiparallel diodes (detailed in Section 6.3.2), nearly eliminating the leakage current though the diodes. The guard buffer output can be accessed through the guard pins (2 and 7). Use the guard pins to protect external components and input traces from possible current leakage paths. The guard buffer is isolated from large capacitive loads that can be present at the guard pins by a nominal 1kΩ resistor. For more on guarding, see Section 7.1.2.

The guard buffer is a rail-to-rail input and output amplifier with the same complementary input stage as the OPA928. Like all rail-to-rail amplifiers, the guard buffer output cannot swing all the way to the rail by a few millivolts. This is particularly important in some special single-supply cases because the input bias performance of the OPA928 is sensitive to small differential voltages across the internal antiparallel diodes; see also Section 7.1.3.