JAJSS74B November   2023  – October 2024 OPA2994-Q1 , OPA994-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Unlimited Capacitive Load Drive
      2. 6.3.2 Common-Mode Voltage Range
      3. 6.3.3 Phase Reversal Protection
      4. 6.3.4 Electrical Overstress
      5. 6.3.5 Overload Recovery
      6. 6.3.6 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

OPA994-Q1 OPA2994-Q1 OPA994-Q1 DBV Package5-Pin SOT-23(Top View)Figure 4-1 OPA994-Q1 DBV Package
5-Pin SOT-23
(Top View)
Table 4-1 Pin Functions: OPA994-Q1
PINTYPE(1)DESCRIPTION
NAMENO.
IN+3INoninverting input
IN–4IInverting input
OUT1OOutput
V+5—Positive (highest) power supply
V–2—Negative (lowest) power supply
(1) I = input, O = output
OPA994-Q1 OPA2994-Q1 OPA2994-Q1 D and DGK#GUID-1C586361-9BD0-4C80-92AC-D7A721DA6D97/GUID-4E78976D-6930-4A1E-81CC-15C6C7EE68C0 Packages:8-Pin SOIC and VSSOP(Top View)Figure 4-2 OPA2994-Q1 D and DGK(1) Packages:
8-Pin SOIC and VSSOP
(Top View)
Table 4-2 Pin Functions: OPA2994-Q1
PINTYPE(2)DESCRIPTION
NAMENO.
IN1+3INoninverting input, channel 1
IN1–2IInverting input, channel 1
IN2+5INoninverting input, channel 2
IN2–6IInverting input, channel 2
OUT11OOutput, channel 1
OUT27OOutput, channel 2
V+8—Positive (highest) power supply
V–4—Negative (lowest) power supply
(1) The DGK (VSSOP, 8) package is preview only.
(2) I = input, O = output