SBOS681C July   2014  – November 2017 OPT3001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Spectral Response: The OPT3001 and Human Eye
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Human Eye Matching
      2. 7.3.2 Automatic Full-Scale Range Setting
      3. 7.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 7.3.4 I2C Bus Overview
        1. 7.3.4.1 Serial Bus Address
        2. 7.3.4.2 Serial Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Automatic Full-Scale Setting Mode
      2. 7.4.2 Interrupt Reporting Mechanism Modes
        1. 7.4.2.1 Latched Window-Style Comparison Mode
        2. 7.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 7.4.2.3 End-of-Conversion Mode
        4. 7.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 7.5 Programming
      1. 7.5.1 Writing and Reading
        1. 7.5.1.1 High-Speed I2C Mode
        2. 7.5.1.2 General-Call Reset Command
        3. 7.5.1.3 SMBus Alert Response
    6. 7.6 Register Maps
      1. 7.6.1 Internal Registers
        1. 7.6.1.1 Register Descriptions
          1. 7.6.1.1.1 Result Register (offset = 00h)
            1. Table 7. Result Register Field Descriptions
          2. 7.6.1.1.2 Configuration Register (offset = 01h) [reset = C810h]
            1. Table 10. Configuration Register Field Descriptions
          3. 7.6.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]
            1. Table 11. Low-Limit Register Field Descriptions
          4. 7.6.1.1.4 High-Limit Register (offset = 03h) [reset = BFFFh]
            1. Table 13. High-Limit Register Field Descriptions
          5. 7.6.1.1.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
            1. Table 14. Manufacturer ID Register Field Descriptions
          6. 7.6.1.1.6 Device ID Register (offset = 7Fh) [reset = 3001h]
            1. Table 15. Device ID Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Interface
      2. 8.1.2 Optical Interface
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Optomechanical Design
        2. 8.2.2.2 Dark Window Selection and Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Soldering and Handling Recommendations
    2. 12.2 DNP (S-PDSO-N6) Mechanical Drawings

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.2 Interrupt Reporting Mechanism Modes

There are two major types of interrupt reporting mechanism modes: latched window-style comparison mode and transparent hysteresis-style comparison mode. The configuration register latch field (L) (see the configuration register, bit 4) controls which of these two modes is used. An end-of-conversion mode is also associated with each major mode type. The end-of-conversion mode is active when the two most significant bits of the threshold low register are set to 11b. The mechanisms report via the flag high and flag low fields, the conversion ready field, and the INT pin.