JAJSEU6A February 2018 – June 2018 OPT3101
PRODUCTION DATA.
The I2C slave interface can be accessed with the SDA_S and SLC_S device pins. The I2C interface supports bus speeds up to 400 kHz. The slave address for this device is 1011A2A1A0. Using the A0, A1, and A2 pins, the address can be configured. By default A0, A1 and A2 are pulled to the AVDD supply and the default address is 1011 111. To change the address, connect these pins to either the AVDD or AVSS supply. The register access can be single R/W or continuous R/W with auto-increment of register address.
FIELD | BIT | DESCRIPTION |
---|---|---|
I2C_CONT_RW | 00h[6] | Enable continuous read/write of registers using device I2C slave |
The individual registers are 24-bit length in this device. However, the register read/write is in chunks of eight bits. After every 8-bit transfer, the slave expects an acknowledgement from the master in the case of read or gives out an acknowledgement in the case of write. Figure 26 shows the I2C timing for register write operation.
For example, to write 0x654321 to any register, the data should be split as three bytes and ordered as follows, 0x21, 0x43, 0x65. The same ordering is true for read mode. The first byte of data received corresponds to [7:0], followed by [15:8] and then followed by [23:16]. Figure 27 shows the different read/write modes.