JAJSMP8C May 2023 – June 2024 OPT4001-Q1
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EXPONENT | RESULT_MSB | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT_MSB | |||||||
R-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | EXPONENT | R | 0h | EXPONENT output. Determines the full-scale range of the light measurement. Used as a scaling factor for lux calculation |
11-0 | RESULT_MSB | R | 0h | Result register MSB (Most significant bits). Used to calculate the MANTISSA representing light level within a given EXPONENT or full-scale range |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT_LSB | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTER | CRC | ||||||
R-0h | R-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESULT_LSB | R | 0h | Result register LSB (Least significant bits). Used to calculate MANTISSA representing light level within a given EXPONENT or full-scale range |
7-4 | COUNTER | R | 0h | Sample counter. Rolling counter which increments for every conversion |
3-0 | CRC | R | 0h | CRC bits. R[19:0]=MANTISSA=((RESULT_MSB<<8)+ RESULT_LSB X[0]=XOR(E[3:0],R[19:0],C[3:0]) XOR of all bits X[1]=XOR(C[1],C[3],R[1],R[3],R[5],R[7],R[9],R[11],R[13],R[15],R[17],R[19],E[1],E[3]) X[2]=XOR(C[3],R[3],R[7],R[11],R[15],R[19],E[3]) X[3]=XOR(R[3],R[11],R[19]) |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EXPONENT_FIFO0 | RESULT_MSB_FIFO0 | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT_MSB_FIFO0 | |||||||
R-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | EXPONENT_FIFO0 | R | 0h | EXPONENT register from FIFO 0 |
11-0 | RESULT_MSB_FIFO0 | R | 0h | RESULT_MSB Register from FIFO 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT_LSB_FIFO0 | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTER_FIFO0 | CRC_FIFO0 | ||||||
R-0h | R-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESULT_LSB_FIFO0 | R | 0h | RESULT_LSB Register from FIFO 0 |
7-4 | COUNTER_FIFO0 | R | 0h | COUNTER Register from FIFO 0 |
3-0 | CRC_FIFO0 | R | 0h | CRC Register from FIFO 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EXPONENT_FIFO1 | RESULT_MSB_FIFO1 | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT_MSB_FIFO1 | |||||||
R-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | EXPONENT_FIFO1 | R | 0h | EXPONENT register from FIFO 1 |
11-0 | RESULT_MSB_FIFO1 | R | 0h | RESULT_MSB Register from FIFO 1 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT_LSB_FIFO1 | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTER_FIFO1 | CRC_FIFO1 | ||||||
R-0h | R-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESULT_LSB_FIFO1 | R | 0h | RESULT_LSB Register from FIFO 1 |
7-4 | COUNTER_FIFO1 | R | 0h | COUNTER Register from FIFO 1 |
3-0 | CRC_FIFO1 | R | 0h | CRC Register from FIFO 1 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EXPONENT_FIFO2 | RESULT_MSB_FIFO2 | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESULT_MSB_FIFO2 | |||||||
R-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | EXPONENT_FIFO2 | R | 0h | EXPONENT register from FIFO 2 |
11-0 | RESULT_MSB_FIFO2 | R | 0h | RESULT_MSB Register from FIFO 2 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESULT_LSB_FIFO2 | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTER_FIFO2 | CRC_FIFO2 | ||||||
R-0h | R-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESULT_LSB_FIFO2 | R | 0h | RESULT_LSB Register from FIFO 2 |
7-4 | COUNTER_FIFO2 | R | 0h | COUNTER Register from FIFO 2 |
3-0 | CRC_FIFO2 | R | 0h | CRC Register from FIFO 2 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
THRESHOLD_L_EXPONENT | THRESHOLD_L_RESULT | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THRESHOLD_L_RESULT | |||||||
R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | THRESHOLD_L_EXPONENT | R/W | 0h | Threshold low register exponent |
11-0 | THRESHOLD_L_RESULT | R/W | 0h | Threshold low register result |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
THRESHOLD_H_EXPONENT | THRESHOLD_H_RESULT | ||||||
R/W-Bh | R/W-Fh | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THRESHOLD_H_RESULT | |||||||
R/W-FFh |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | THRESHOLD_H_EXPONENT | R/W | Bh | Threshold high register exponent |
11-0 | THRESHOLD_H_RESULT | R/W | FFFh | Threshold high register result |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
QWAKE | 0 | RANGE | CONVERSION_TIME | ||||
R/W-0h | R/W-0h | R/W-Ch | R/W-2h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CONVERSION_TIME | OPERATING_MODE | LATCH | INT_POL | FAULT_COUNT | |||
R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-15 | QWAKE | R/W | 0h | Quick wake-up from standby in one-shot mode by not powering down all circuits. Applicable only in one-shot mode and helps get out of standby mode faster with penalty in power consumption compared to full standby mode. |
14-14 | 0 | R/W | 0h | Must read or write 0 |
13-10 | RANGE | R/W | Ch | Controls the full-scale light level range of the device. The format of this register is same as the EXPONENT register for all values from 0 to 8. PicoStar™ variant: 0 : 328lux 1 : 655lux 2 : 1.3klux 3 : 2.6klux 4 : 5.2klux 5 : 10.5klux 6 : 21klux 7 : 42klux 8 : 83klux 12 : Auto-Range USON variant: 0 : 419lux 1 : 839lux 2 : 1.7klux 3 : 3.3klux 4 : 6.7klux 5 : 13.4klux 6 : 26.7klux 7 : 53.7klux 8 : 107klux 12 : Auto-Range |
9-6 | CONVERSION_TIME | R/W | 8h | Controls the device conversion time 0 : 600µs 1 : 1ms 2 : 1.8ms 3 : 3.4ms 4 : 6.5ms 5 : 12.7ms 6 : 25ms 7 : 50ms 8 : 100ms 9 : 200ms 10 : 400ms 11 : 800ms |
5-4 | OPERATING_MODE | R/W | 0h | Controls device mode of operation 0 : Power-down 1 : Forced auto-range One-shot 2 : One-shot 3 : Continuous |
3-3 | LATCH | R/W | 1h | Controls the functionality of the interrupt reporting mechanisms for INT pin (USON variant only) for the threshold detection logic. |
2-2 | INT_POL | R/W | 0h | Controls the polarity or active state of the INT pin (USON variant only). 0 : Active Low 1 : Active High |
1-0 | FAULT_COUNT | R/W | 0h | Fault count register instructs the device as to how many consecutive fault events are required to trigger the threshold mechanisms: the flag high (FLAG_H) and the flag low (FLAG_L) registers. 0 : One fault Count 1 : Two Fault Counts 2 : Four Fault Counts 3 : Eight Fault Counts |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | INT_DIR | INT_CFG | 0 | I2C_BURST | |
R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-1h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | 1024 | R/W | 400h | Must read or write 1024 |
4-4 | INT_DIR | R/W | 1h | Determines the direction of the INT pin (USON variant only). 0 : Input 1 : Output |
3-2 | INT_CFG | R/W | 0h | Controls the output interrupt mechanism after end of conversion (USON variant only). 0 : SMBUS Alert 1 : INT Pin asserted after every conversion 2: Invalid 3: INT pin asserted after every 4 conversions (FIFO full) |
1-1 | 0 | R/W | 0h | Must read or write 0 |
0-0 | I2C_BURST | R/W | 1h | When set, enables I2C burst mode minimizing I2C read cycles by auto incrementing read register pointer by 1 after every register read |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | OVERLOAD_FLAG | CONVERSION_READY_FLAG | FLAG_H | FLAG_L |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | 0 | R/W | 0h | Must read or write 0 |
3-3 | OVERLOAD_FLAG | R | 0h | Indicates when an overflow condition occurs in the data conversion process, typically because the light illuminating the device exceeds the full-scale range. |
2-2 | CONVERSION_READY_FLAG | R | 0h | Conversion ready flag indicates when a conversion completes. The flag is set to 1 at the end of a conversion and is cleared (set to 0) when register address 0xC is either read or written with any non-zero value 0 : Conversion in progress 1 : Conversion is complete |
1-1 | FLAG_H | R | 0h | Flag high register identifies that the result of a conversion is measurement than a specified level of interest. FLAG_H is set to 1 when the result is larger than the level in the THRESHOLD_H_EXPONENT and THRESHOLD_H_RESULT registers for a consecutive number of measurements defined by the FAULT_COUNT register. |
0-0 | FLAG_L | R | 0h | Flag low register identifies that the result of a measurement is smaller than a specified level of interest. FL is set to 1 when the result is smaller than the level in the THRESHOLD_LOW_EXPONENT and THRESHOLD_L_RESULT registers for a consecutive number of measurements defined by the FAULT_COUNT register. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
0 | 0 | DIDL | DIDH | ||||
R/W-0h | R/W-0h | R-0h | R-1h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIDH | |||||||
R-21h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | 0 | R/W | 0h | Must read or write 0 |
13-12 | DIDL | R | 0h | Device ID L |
11-0 | DIDH | R | 121h | Device ID H |