JAJSNK9A December   2021  – December 2022 OPT4001

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. 概要 (続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Spectral Matching to Human Eye
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Output Register CRC and Counter
        1. 8.3.3.1 Output Sample Counter
        2. 8.3.3.2 Output CRC
      4. 8.3.4 Output Register FIFO
      5. 8.3.5 Threshold Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
      2. 8.4.2 Interrupt Modes of Operation
      3. 8.4.3 Light Range Selection
      4. 8.4.4 Selecting Conversion Time
      5. 8.4.5 Light Measurement in Lux
      6. 8.4.6 Light Resolution
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Overview
        1. 8.5.1.1 Serial Bus Address
        2. 8.5.1.2 Serial Interface
      2. 8.5.2 Writing and Reading
        1. 8.5.2.1 High-Speed I2C Mode
        2. 8.5.2.2 Burst Read Mode
        3. 8.5.2.3 General-Call Reset Command
        4. 8.5.2.4 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 ALL Register Map
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Electrical Interface
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Optical Interface
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Optomechanical Design (PicoStar Variant)
          2. 9.2.1.2.2 Optomechanical Design (SOT-5X3 Variant)
        3. 9.2.1.3 Application Curves (PicoStar Variant)
    3. 9.3 Do's and Don'ts
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
        1. 9.5.2.1 Soldering and Handling Recommendations (SOT-5X3 Variant)
        2. 9.5.2.2 Soldering and Handling Recommendations (PicoStar Variant)
          1. 9.5.2.2.1 Solder Paste
          2. 9.5.2.2.2 Package Placement
          3. 9.5.2.2.3 Reflow Profile
          4. 9.5.2.2.4 Special Flexible Printed-Circuit Board (FPCB) Recommendations
          5. 9.5.2.2.5 Rework Process
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Interface

The electrical interface is quite simple, as illustrated in Figure 9-1 below. Connect the OPT4001 I2C SDA and SCL pins to the same pins of an applications processor, micro controller, or other digital processor. If that digital processor requires an interrupt resulting from an event of interest from theOPT4001, then connect the INT pin to either an interrupt or general-purpose I/O pin of the processor (Only for the SOT-5X3). There are multiple uses for this INT pin, including triggering a measurement on one-shot mode, signaling the system to wake up from low-power mode, processing other tasks while waiting for an ambient light event of interest, or alerting the processor that a sample is ready to be read.. Connect pullup resistors between a power supply appropriate for digital communication and the SDA and SCL pins (because the pins have open-drain output structures). If the INT pin is used, connect a pullup resistor to the INT pin. A typical value for these pullup resistors is 10 kΩ. The resistor choice can be optimized in conjunction to the bus capacitance to balance the system speed, power, noise immunity, and other requirements.

Figure 9-1 Typical Application Schematic

The power supply and grounding considerations are discussed in the Section 9.4.

Although spike suppression is integrated in the SDA and SCL pin circuits, use proper layout practices to minimize the amount of coupling into the communication lines. One possible introduction of noise occurs from capacitively coupling signal edges between the two communication lines themselves. Another possible noise introduction comes from other switching noise sources present in the system, especially for long communication lines. In noisy environments, shield communication lines to reduce the possibility of unintended noise coupling into the digital I/O lines that can be incorrectly interpreted.