The time-of-flight controller (TFC) is a high-performance, 3D time-of-flight (ToF) sensor companion device that computes the depth data from the digitized sensor data. Depth data are output via a programmable complementary metal-oxide-semiconductor (CMOS) parallel interface.
In addition to depth data, the TFC provides auxiliary information consisting of amplitude, ambient, and flags for each pixel. This information can be used to implement filters and masks and to dynamically control the system configuration for the intended performance.
The TFC supports a wide range of binning and ROI options that help optimize the data throughput that must be handled.
The 9-mm × 9-mm NFBGA package enables small form-factor, 3D, ToF systems that can be embedded into a variety of end equipment.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
OPT9221 | NFBGA (256) | 9.00 mm × 9.00 mm |
Changes from * Revision (June 2015) to A Revision
PIN | I/O | I/O STANDARD | I/O BANK | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
BOOT_0 | H13 | Input | 2.5 V | – | Boot configuration pin 0. Tie to VCC or to GND. |
BOOT_1 | H12 | Input | 2.5 V | – | Boot configuration pin 1. Tie to VCC or to GND. |
BOOT_2 | G12 | Input | 2.5 V | – | Boot configuration pin 2. Tie to VCC or to GND. |
CAP_BIT_CLKM | M16 | Input | LVDS | VCCIO5 | Sensor data bit clk |
CAP_BIT_CLKP | M15 | Input | LVDS | VCCIO5 | Sensor data bit clk |
CAP_DATA_DIFF_0M | N16 | Input | LVDS | VCCIO5 | Sensor differential data ch 0 |
CAP_DATA_DIFF_0P | N15 | Input | LVDS | VCCIO5 | Sensor differential data ch 0 |
CAP_DATA_DIFF_1M | K16 | Input | LVDS | VCCIO5 | Sensor differential data ch 1 |
CAP_DATA_DIFF_1P | K15 | Input | LVDS | VCCIO5 | Sensor differential data ch 1 |
CAP_DATA_SUM_M | J16 | Input | LVDS | VCCIO5 | Sensor common mode data |
CAP_DATA_SUM_P | J15 | Input | LVDS | VCCIO5 | Sensor common mode data |
CAP_FRM_CLKM | P16 | Input | LVDS | VCCIO5 | Sensor sample clk |
CAP_FRM_CLKP | R16 | Input | LVDS | VCCIO5 | Sensor sample clk |
COMP_MOD_FB | E16 | Input | 3.3 V | VCCIO6 | Feedback signal from the external illumination modulation feedback comparator. |
COMP_MOD_REF | F16 | Output | 3.3 V | VCCIO6 | Reference modulation signal for measuring external illumination modulation feedback comparator delay. |
DDR2_ADDR_0 | L11 | Output | SSTL-18 Class I | VCCIO4 | DDR address signal 0 |
DDR2_ADDR_1 | L9 | Output | SSTL-18 Class I | VCCIO4 | DDR address signal 1 |
DDR2_ADDR_2 | K10 | Output | SSTL-18 Class I | VCCIO4 | DDR address signal 2 |
DDR2_ADDR_3 | K9 | Output | SSTL-18 Class I | VCCIO4 | DDR address signal 3 |
DDR2_ADDR_4 | M11 | Output | SSTL-18 Class I | VCCIO4 | DDR address signal 4 |
DDR2_ADDR_5 | M9 | Output | SSTL-18 Class I | VCCIO4 | DDR address signal 5 |
DDR2_ADDR_6 | L10 | Output | SSTL-18 Class I | VCCIO4 | DDR address signal 6 |
DDR2_ADDR_7 | T6 | Output | SSTL-18 Class I | VCCIO3 | DDR address signal 7 |
DDR2_ADDR_8 | N11 | Output | SSTL-18 Class I | VCCIO4 | DDR address signal 8 |
DDR2_ADDR_9 | P9 | Output | SSTL-18 Class I | VCCIO4 | DDR address signal 9 |
DDR2_ADDR_10 | N3 | Output | SSTL-18 Class I | VCCIO3 | DDR address signal 10 |
DDR2_ADDR_11 | M10 | Output | SSTL-18 Class I | VCCIO4 | DDR address signal 11 |
DDR2_ADDR_12 | T5 | Output | SSTL-18 Class I | VCCIO3 | DDR address signal 12 |
DDR2_BA_0 | R4 | Output | SSTL-18 Class I | VCCIO3 | DDR bank signal |
DDR2_BA_1 | T4 | Output | SSTL-18 Class I | VCCIO3 | DDR bank signal |
DDR2_CASZ | T11 | Output | SSTL-18 Class I | VCCIO4 | DDR CAS |
DDR2_CKE | T2 | Output | SSTL-18 Class I | VCCIO3 | DDR clock enable |
DDR2_CLK_0 | R14 | Output | SSTL-18 Class I | VCCIO4 | DDR clock |
DDR2_CLKz_0 | P14 | Output | SSTL-18 Class I | VCCIO4 | DDR clock |
DDR2_CSZ | R13 | Output | SSTL-18 Class I | VCCIO4 | DDR chip select |
DDR2_DM_0 | P3 | Output | SSTL-18 Class I | VCCIO3 | DDR data mask 0 |
DDR2_DM_1 | M8 | Output | SSTL-18 Class I | VCCIO3 | DDR data mask 1 |
DDR2_DQ_0 | L7 | Bidir | SSTL-18 Class I | VCCIO3 | DDR data 15 |
DDR2_DQ_1 | N5 | Bidir | SSTL-18 Class I | VCCIO3 | DDR data 14 |
DDR2_DQ_2 | R6 | Bidir | SSTL-18 Class I | VCCIO3 | DDR data 13 |
DDR2_DQ_3 | N6 | Bidir | SSTL-18 Class I | VCCIO3 | DDR data 12 |
DDR2_DQ_4 | R5 | Bidir | SSTL-18 Class I | VCCIO3 | DDR data 11 |
DDR2_DQ_5 | R7 | Bidir | SSTL-18 Class I | VCCIO3 | DDR data 10 |
DDR2_DQ_6 | R3 | Bidir | SSTL-18 Class I | VCCIO3 | DDR data 9 |
DDR2_DQ_7 | L8 | Bidir | SSTL-18 Class I | VCCIO3 | DDR data 8 |
DDR2_DQ_8 | R12 | Bidir | SSTL-18 Class I | VCCIO4 | DDR data 7 |
DDR2_DQ_9 | N9 | Bidir | SSTL-18 Class I | VCCIO4 | DDR data 6 |
DDR2_DQ_10 | R11 | Bidir | SSTL-18 Class I | VCCIO4 | DDR data 5 |
DDR2_DQ_11 | R10 | Bidir | SSTL-18 Class I | VCCIO4 | DDR data 4 |
DDR2_DQ_12 | P8 | Bidir | SSTL-18 Class I | VCCIO3 | DDR data 3 |
DDR2_DQ_13 | T14 | Bidir | SSTL-18 Class I | VCCIO4 | DDR data 2 |
DDR2_DQ_14 | N8 | Bidir | SSTL-18 Class I | VCCIO3 | DDR data 1 |
DDR2_DQ_15 | T13 | Bidir | SSTL-18 Class I | VCCIO4 | DDR data 0 |
DDR2_DQS_0 | M7 | Output | SSTL-18 Class I | VCCIO3 | DDR data strobe |
DDR2_DQS_1 | T7 | Output | SSTL-18 Class I | VCCIO3 | DDR data strobe |
DDR2_ODT_0 | T15 | Bidir | SSTL-18 Class I | VCCIO4 | DDR on die termination |
DDR2_RASZ | T12 | Output | SSTL-18 Class I | VCCIO4 | DDR RAS |
DDR2_REF_0 | T3 | Input | Analog | – | DDR reference, tie to 0.9 V |
DDR2_REF_1 | P6 | Input | Analog | – | DDR reference, tie to 0.9 V |
DDR2_REF_2 | P11 | Input | Analog | – | DDR reference, tie to 0.9 V |
DDR2_REF_3 | N12 | Input | Analog | – | DDR reference, tie to 0.9 V |
DDR2_WEZ | T10 | Output | SSTL-18 Class I | VCCIO4 | DDR write enable |
DEBUG | D1 | Bidir | 1.8 V | VCCIO1 | TI proprietary debug port. Pullup by 10 kΩ. |
FE | L6 | Output | 1.8 V | VCCIO2 | Marks the end of a frame |
GND | B2 | Power | – | – | Digital ground |
GND | B15 | Power | – | – | Digital ground |
GND | C5 | Power | – | – | Digital ground |
GND | C12 | Power | – | – | Digital ground |
GND | D7 | Power | – | – | Digital ground |
GND | D10 | Power | – | – | Digital ground |
GND | E2 | Power | – | – | Digital ground |
GND | E4 | Power | – | – | Digital ground |
GND | E13 | Power | – | – | Digital ground |
GND | F6 | Power | – | – | Digital ground |
GND | F10 | Power | – | – | Digital ground |
GND | G4 | Power | – | – | Digital ground |
GND | G13 | Power | – | – | Digital ground |
GND | H7 | Power | – | – | Digital ground |
GND | H8 | Power | – | – | Digital ground |
GND | H9 | Power | – | – | Digital ground |
GND | H10 | Power | – | – | Digital ground |
GND | H15 | Power | – | – | Digital ground |
GND | H16 | Power | – | – | Digital ground |
GND | J7 | Power | – | – | Digital ground |
GND | J8 | Power | – | – | Digital ground |
GND | J9 | Power | – | – | Digital ground |
GND | J10 | Power | – | – | Digital ground |
GND | J11 | Power | – | – | Digital ground |
GND | K4 | Power | – | – | Digital ground |
GND | K8 | Power | – | – | Digital ground |
GND | K13 | Power | – | – | Digital ground |
GND | M4 | Power | – | – | Digital ground |
GND | M13 | Power | – | – | Digital ground |
GND | N7 | Power | – | – | Digital ground |
GND | N10 | Power | – | – | Digital ground |
GND | P5 | Power | – | – | Digital ground |
GND | P12 | Power | – | – | Digital ground |
GND | R2 | Power | – | – | Digital ground |
GND | R15 | Power | – | – | Digital ground |
GNDA1 | M5 | Power | – | – | Analog ground |
GNDA2 | E12 | Power | – | – | Analog ground |
GNDA3 | E5 | Power | – | – | Analog ground |
GNDA4 | M12 | Power | – | – | Analog ground |
GPI_0 | F9 | Input | 1.8 V | VCCIO7 | Sensor general purpose pin |
GPI_1 | E9 | Input | 1.8 V | VCCIO7 | Sensor general purpose pin |
GPO_1 | B3 | Output | 1.8 V | VCCIO8 | General purpose output |
GPO_2 | A3 | Output | 1.8 V | VCCIO8 | General purpose output |
GPO_3 | A2 | Output | 1.8 V | VCCIO8 | General purpose output |
GPO_0 | A4 | Output | 1.8 V | VCCIO8 | General purpose output |
HD/BD | J2 | Output | 1.8 V | VCCIO2 | Indicates the row boundary or block boundary |
HD_QD | A11 | Input | 1.8 V | VCCIO7 | Sensor HD |
ILLUM_FB | B16 | Input | 3.3 V | VCCIO6 | Comparator output feedback to TFC |
ILLUM_MOD_FB | E15 | Input | 3.3 V | VCCIO6 | Illumination modulation signal input. Connect to ILLUM_P/M of the OPT8241 sensor. |
ILLUM_REF | F13 | Output | 3.3 V | VCCIO6 | Comparator reference signal |
ILLUM_SW_1 | C16 | Output | 3.3 V | VCCIO6 | DCDC control signal 1 |
ILLUM_SW_2 | C15 | Output | 3.3 V | VCCIO6 | DCDC control signal 2 |
INT_OUT | G2 | Output | 1.8 V | VCCIO1 | Interrupt to external host |
INT_PMIC | G5 | Input | 1.8 V | VCCIO1 | Interrupt from PMIC |
IO_MOD_REF | F15 | Output | 3.3 V | VCCIO6 | Reference modulation signal from the TFC for measuring TFC I/O delay |
I2C_MAS_SCL | D8 | Output | 1.8 V | VCCIO8 | I2C master clk |
I2C_MAS_SDA | C8 | Bidir | 1.8 V | VCCIO8 | I2C master data |
I2C_SCL_SENSOR | D9 | Output | 1.8 V | VCCIO7 | Dedicated I2C for sensor - clock |
I2C_SDA_SENSOR | C9 | Bidir | 1.8 V | VCCIO7 | Dedicated I2C for sensor - data |
I2C_SLV_SCL | F1 | Input | 1.8 V | VCCIO1 | I2C slave clk |
I2C_SLV_SDA | F2 | Bidir | 1.8 V | VCCIO1 | I2C slave data |
OP_CLK | K5 | Output | 1.8 V | VCCIO2 | Output data clock |
OP_CS | K6 | Output | 1.8 V | VCCIO2 | Indicates the validity of the data output. Useful for SPI mode. |
OP_DATA_0 | R1 | Output | 1.8 V | VCCIO2 | Output data bit 0 |
OP_DATA_1 | P1 | Output | 1.8 V | VCCIO2 | Output data bit 1 |
OP_DATA_2 | P2 | Output | 1.8 V | VCCIO2 | Output data bit 2 |
OP_DATA_3 | N1 | Output | 1.8 V | VCCIO2 | Output data bit 3 |
OP_DATA_4 | N2 | Output | 1.8 V | VCCIO2 | Output data bit 4 |
OP_DATA_5 | L1 | Output | 1.8 V | VCCIO2 | Output data bit 5 |
OP_DATA_6 | L2 | Output | 1.8 V | VCCIO2 | Output data bit 6 |
OP_DATA_7 | L4 | Output | 1.8 V | VCCIO2 | Output data bit 7 |
OVERFLOW | L3 | Input | 1.8 V | VCCIO2 | Used to indicate failure in flow control. |
PHASE_AUX | K2 | Output | 1.8 V | VCCIO2 | Indicates the type of data on the output bus. |
READY | M1 | Input | 1.8 V | VCCIO2 | Used to achieve flow control of the output data. |
RESETZ | C2 | Input | 1.8 V | VCCIO1 | Global reset for the TFC |
RSVD | A6 | Bidir | 1.8 V | VCCIO8 | Reserved. Leave unconnected. |
RSVD | B4 | Bidir | 3.3 V | VCCIO6 | Leave unconnected |
RSVD | B5 | Bidir | 1.8 V | VCCIO8 | Reserved. Leave unconnected. |
RSVD | B6 | Bidir | 1.8 V | VCCIO8 | Reserved. Leave unconnected. |
RSVD | B10 | Bidir | 1.8 V | VCCIO7 | Leave unconnected |
RSVD | B11 | Bidir | 1.8 V | VCCIO7 | Leave unconnected |
RSVD | B12 | Bidir | 1.8 V | VCCIO7 | Leave unconnected |
RSVD | B13 | Bidir | 1.8 V | VCCIO7 | Leave unconnected |
RSVD | C3 | Bidir | 1.8 V | VCCIO8 | Leave unconnected |
RSVD | C6 | Bidir | 1.8 V | VCCIO8 | Reserved. Leave unconnected. |
RSVD | C11 | Bidir | 1.8 V | VCCIO7 | Leave unconnected |
RSVD | C14 | Bidir | 1.8 V | VCCIO7 | Leave unconnected |
RSVD | D3 | Bidir | 1.8 V | VCCIO8 | Reserved. Leave unconnected. |
RSVD | D5 | Bidir | 1.8 V | VCCIO8 | Reserved. Leave unconnected. |
RSVD | D6 | Bidir | 1.8 V | VCCIO8 | Reserved. Leave unconnected. |
RSVD | D11 | Bidir | 1.8 V | VCCIO7 | Leave unconnected |
RSVD | D12 | Bidir | 1.8 V | VCCIO7 | Leave unconnected |
RSVD | D15 | Bidir | 3.3 V | VCCIO6 | Leave unconnected |
RSVD | D16 | Bidir | 3.3 V | VCCIO6 | Leave unconnected |
RSVD | E10 | Bidir | 1.8 V | VCCIO7 | Leave unconnected |
RSVD | E11 | Bidir | 1.8 V | VCCIO7 | Leave unconnected |
RSVD | F3 | Bidir | 1.8 V | VCCIO1 | Leave unconnected |
RSVD | F14 | Bidir | 3.3 V | VCCIO6 | Leave unconnected |
RSVD | G1 | Bidir | 1.8 V | VCCIO1 | Leave unconnected |
RSVD | G11 | Bidir | 3.3 V | VCCIO6 | Leave unconnected |
RSVD | G15 | Bidir | 3.3 V | VCCIO6 | Leave unconnected |
RSVD | J1 | Output | 1.8 V | VCCIO2 | Reserved |
RSVD | J12 | Bidir | 2.5 V | VCCIO5 | Leave unconnected |
RSVD | J13 | Bidir | 2.5 V | VCCIO5 | Leave unconnected |
RSVD | J14 | Bidir | 2.5 V | VCCIO5 | Leave unconnected |
RSVD | K12 | Bidir | 2.5 V | VCCIO5 | Leave unconnected |
RSVD | L13 | Bidir | 2.5 V | VCCIO5 | Leave unconnected |
RSVD | L16 | Bidir | 2.5 V | VCCIO5 | Leave unconnected |
RSVD | M6 | Bidir | 1.8 V | VCCIO3 | Leave unconnected |
RSVD | N14 | Bidir | 2.5 V | VCCIO5 | Leave unconnected |
RSVD | P15 | Bidir | 2.5 V | VCCIO5 | Leave unconnected |
RSVD_IN | A8 | Input | 1.8 V | VCCIO8 | Tie to GND |
RSVD_IN | A9 | Input | 1.8 V | VCCIO7 | Tie to GND |
RSVD_IN | B8 | Input | 1.8 V | VCCIO8 | Tie to GND |
RSVD_IN | B9 | Input | 1.8 V | VCCIO7 | Tie to GND |
RSVD_IN | L14 | Input | Analog | VCCIO5 | Tie to 2.5 V |
RSVD_IN | L15 | Input | Analog | VCCIO5 | Tie to 2.5 V |
RSVD_IN | M2 | Input | 1.8 V | VCCIO2 | Tie to GND |
RSVD_IN | R8 | Input | 1.8 V | VCCIO3 | Tie to GND |
RSVD_IN | R9 | Input | 1.8 V | VCCIO4 | Tie to GND |
RSVD_IN | T8 | Input | 1.8 V | VCCIO3 | Tie to GND |
RSVD_IN | T9 | Input | 1.8 V | VCCIO4 | Tie to GND |
SENSOR_CLK | B14 | Output | 1.8 V | VCCIO7 | Sensor main clock |
SENSOR_DEMOD_CLK | A14 | Output | 1.8 V | VCCIO7 | Demod clock for test |
SENSOR_RSTZ | D14 | Output | 1.8 V | VCCIO7 | Sensor reset |
SLEEP | B1 | Input | 1.8 V | VCCIO1 | Puts the TFC in standby mode when enabled |
SYSCLK_IN | E1 | Input | 1.8 V | VCCIO1 | Main system clock input |
TIC_C | H3 | Input | 2.5 V | – | Reserved. Needs external pull-down resistor of 10 kΩ |
TIC_CEZ | J3 | Input | 1.8 V | VCCIO1 | If high, TFC releases the control of configuration pins. In slave boot modes, tie to ground. |
TIC_CLK | H1 | Input | 1.8 V | VCCIO1 | Configuration data clock |
TIC_CONFIGZ | H5 | Input | 1.8 V | VCCIO1 | Used to start firmware load operation |
TIC_CONF_DONE | H14 | Output | Open Drain | VCCIO6 | Used to indicate end of firmware load operation |
TIC_CSOZ | D2 | Output | 1.8 V | VCCIO1 | In master serial boot mode, Used by TFC to load firmware from EEPROM as chip select pin. |
TIC_DATA_0 | H2 | Input | 1.8 V | VCCIO1 | Configuration data pin 0 |
TIC_DATA_1/ASDO | C1 | Bidir | 1.8 V | VCCIO1 | Used as output in master serial boot mode to communicate to firmware EEPROM as data-out pin. Input in passive parallel boot mode. |
TIC_DATA_2 | E8 | Input | 1.8 V | VCCIO8 | Used only in Passive Parallel Boot mode. Tie to GND otherwise. |
TIC_DATA_3 | F8 | Input | 1.8 V | VCCIO8 | Used only in Passive Parallel Boot mode. Tie to GND otherwise. |
TIC_DATA_4 | B7 | Input | 1.8 V | VCCIO8 | Used only in Passive Parallel Boot mode. Tie to GND otherwise. |
TIC_DATA_5 | E7 | Input | 1.8 V | VCCIO8 | Used only in Passive Parallel Boot mode. Tie to GND otherwise. |
TIC_DATA_6 | E6 | Input | 1.8 V | VCCIO8 | Used only in Passive Parallel Boot mode. Tie to GND otherwise. |
TIC_DATA_7 | A5 | Input | 1.8 V | VCCIO8 | Used only in Passive Parallel Boot mode. Tie to GND otherwise. |
TIC_I | H4 | Input | 2.5 V | – | Reserved. Needs external pull-up resistor of 10 kΩ to 2.5 V |
TIC_INIT_DONE | G16 | Output | Open Drain | VCCIO1 | Used to indicate end of TFC initialization. |
TIC_O | J4 | Output | 2.5 V | – | Reserved. Leave unconnected. |
TIC_S | J5 | Input | 2.5 V | – | Reserved. Needs external pull-up resistor of 10 kΩ to 2.5 V |
TIC_STATUSZ | F4 | Output | Open Drain | VCCIO1 | Used to indicate status of firmware load operation |
VCCA1 | L5 | Power | – | – | 2.5-V supply |
VCCA2 | F12 | Power | – | – | 2.5-V supply |
VCCA3 | F5 | Power | – | – | 2.5-V supply |
VCCA4 | L12 | Power | – | – | 2.5-V supply |
VCCD_PLL1 | N4 | Power | – | – | 1.2-V supply |
VCCD_PLL2 | D13 | Power | – | – | 1.2-V supply |
VCCD_PLL3 | D4 | Power | – | – | 1.2-V supply |
VCCD_PLL4 | N13 | Power | – | – | 1.2-V supply |
VCCINT | F7 | Power | – | – | 1.2-V supply |
VCCINT | F11 | Power | – | – | 1.2-V supply |
VCCINT | G6 | Power | – | – | 1.2-V supply |
VCCINT | G7 | Power | – | – | 1.2-V supply |
VCCINT | G8 | Power | – | – | 1.2-V supply |
VCCINT | G9 | Power | – | – | 1.2-V supply |
VCCINT | G10 | Power | – | – | 1.2-V supply |
VCCINT | H6 | Power | – | – | 1.2-V supply |
VCCINT | H11 | Power | – | – | 1.2-V supply |
VCCINT | J6 | Power | – | – | 1.2-V supply |
VCCINT | K7 | Power | – | – | 1.2-V supply |
VCCINT | K11 | Power | – | – | 1.2-V supply |
VCCIO1 | E3 | Power | – | – | 1.8-V supply |
VCCIO1 | G3 | Power | – | – | 1.8-V supply |
VCCIO2 | K3 | Power | – | – | 1.8-V supply |
VCCIO2 | M3 | Power | – | – | 1.8-V supply |
VCCIO3 | P4 | Power | – | – | 1.8-V supply |
VCCIO3 | P7 | Power | – | – | 1.8-V supply |
VCCIO3 | T1 | Power | – | – | 1.8-V supply |
VCCIO4 | P10 | Power | – | – | 1.8-V supply |
VCCIO4 | P13 | Power | – | – | 1.8-V supply |
VCCIO4 | T16 | Power | – | – | 1.8-V supply |
VCCIO5 | K14 | Power | – | – | 2.5-V supply |
VCCIO5 | M14 | Power | – | – | 2.5-V supply |
VCCIO6 | E14 | Power | – | – | 3.3-V supply |
VCCIO6 | G14 | Power | – | – | 3.3-V supply |
VCCIO7 | A16 | Power | – | – | 1.8-V supply |
VCCIO7 | C10 | Power | – | – | 1.8-V supply |
VCCIO7 | C13 | Power | – | – | 1.8-V supply |
VCCIO8 | A1 | Power | – | – | 1.8-V supply |
VCCIO8 | C4 | Power | – | – | 1.8-V supply |
VCCIO8 | C7 | Power | – | – | 1.8-V supply |
VD | K1 | Output | 1.8 V | VCCIO2 | Indicates the frame boundary |
VD_FR | A13 | Input | 1.8 V | VCCIO7 | Sensor Frame VD |
VD_IN | A7 | Input | 1.8 V | VCCIO1 | External Sync input |
VD_QD | A10 | Input | 1.8 V | VCCIO7 | Sensor Quad VD |
VD_SF | A12 | Input | 1.8 V | VCCIO7 | Sensor Sub-Frame VD |
VSYNC_OUT | A15 | Output | 1.8 V | VCCIO7 | Sensor Sync input |