SCPS144 Data sheet

SCPS144C May 2006 – May 2015 P82B96

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

D|8
- MSOI002K
PW|8
- MPDS568
DGK|8
- MPDS028E
P|8
- MPDI001B

サーマルパッド・メカニカル・データ

発注情報

9 Detailed Description

9.1 Overview

The P82B96 is a bus buffer that supports bidirectional data transfer between an I²C bus and a range of other bus configurations with different voltage and current levels.

One of the advantages of the P82B96 is that it supports longer cables/traces and allows for more devices per I²C bus because it can isolate bus capacitance such that the total loading (devices and trace lengths) of the new bus or remote I²C nodes are not apparent to other I²C buses (or nodes). The restrictions on the number of I²C devices in a system due to capacitance, or the physical separation between them, are greatly improved.

The P82B96 is able to provide galvanic isolation (optocoupling) or use balanced transmission lines (twisted pairs), because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be connected directly (without causing bus latching), to provide an bidirectional signal line with I²C properties (open-drain driver). Likewise, the Ty and Ry signals may also be connected together to provide an bidirectional signal line with I²C properties (open-drain driver). This allows for a simple communication design, saving design time and costs.

Two or more Sx or Sy I/Os must not be connected to each other on the same node. The P82B96 design does not support this configuration. Bidirectional I²C signals do not have a direction control pin so, instead, slightly different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A standard I²C low applied at the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a standard I²C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation.

The Sx/Sy side of the P82B96 is intended for I²C logic voltage levels of I²C master and slave devices or Tx/Rx signals of a second P82B96, if required. If Rx and Tx are connected, Sx can function as either the SDA or SCL line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multi-point configuration (multiple P82B96 devices share the same Tx/Rx and Ty/Ry nodes) with the Tx/Rx and Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices.

In any design, the Sx pins of different devices should never be linked, because the resulting system would be very susceptible to induced noise and would not support all I²C operating modes.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Sx and Sy

The I²C pins, Sx and Sy, are designed to interface directly with an I²C bus. The logic threshold-voltage levels on the I²C bus are independent of the supply V_CC. The maximum I²C bus supply voltage is 15 V, and the specified static sink current is 3 mA.

Sx and Sy have two identical buffers. Each buffer is made up of two logic signal paths. The first one, named Tx or Ty, is a forward path from the I²C interface pin, which drives the buffered bus. The second one, named Rx or Ry, is a reverse signal path from the buffered bus input to drive the I²C bus interface.

There are two purposes for these paths: to sense the voltage state of the I²C pin (Sx or Sy) and transmit this state to Tx or Ty, respectively, and to detect the state of the Rx or Ry and pull the I²C pin low when Rx or Ry is low.

9.3.2 Tx and Ty

Tx and Ty are open-collector outputs without ESD protection diodes to V_CC. Each pin may be connected through a pullup resistor to a supply voltage in excess of V_CC, as long as the 15-V rating is not exceeded. Tx and Ty have a larger current-sinking capability than a standard I²C device and can sink a static current of greater than 30 mA. They also have dynamic pulldown capability of 100-mA, typically.

A logic low is transmitted to Tx or Ty only when the voltage at the I²C pin (Sx or Sy) is less than 0.6 V. A logic low at Rx or Ry causes the I²C bus (Sx or Sy) to be pulled to a logic low level in accordance with I²C requirements (maximum 1.5 V in 5-V applications), but not low enough to be looped back to the Tx or Ty output and cause the buffer to latch low.

The minimum low level that the P82B96 can achieve on the I²C bus by a low at Rx or Ry typically is 0.8 V.

If V_CC fails, neither the I²C pins nor the Tx or Ty outputs are held low. Their open-collector configuration allows them to be pulled up to the rated maximum of 15 V without V_CC present. The input configuration on Sx, Sy, Rx, and Ry also presents no loading of external signals when V_CC is not present. This ensures that communication on the main I²C bus can continue if the P82B96 has no supply.

The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 4 pF for all bus voltages and supply voltages, including V_CC = 0 V.

9.3.3 Long Cable Length

The P82B96 supports 400 pF on the main I2C bus (Sx/Sy side) and up to 4000 pF on the transmission side (Tx/Ty). This allows for longer cables to be used due to the significant increase in capacitance allowed by the device.

9.4 Device Functional Modes

The P82B96 begins functioning once V_CC reaches 2 V. When V_CC is low, the P82B96 does not hold the Sx/Sy pins low, which ensures I²C communication can continue between other devices on the bus while the V_CC is low.