JAJSOE5H April   2006  – March 2022 PCA9536

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Powered-Up
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
      4. 8.6.4 Bus Transactions
        1. 8.6.4.1 Writes
        2. 8.6.4.2 Reads
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Minimizing ICC When I/Os Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Errata
    2. 10.2 System Impact
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
MINMAXUNIT
Standard Mode
fsclI2C clock frequency0100kHz
tschI2C clock high time4μs
tsclI2C clock low time4.7μs
tspI2C spike time50ns
tsdsI2C serial-data setup time250ns
tsdhI2C serial-data hold time0ns
ticrI2C input rise time1000ns
ticfI2C input fall time300ns
tocfI2C output fall time, 10-pF to 400-pF bus300ns
tbufI2C bus free time between Stop and Start4.7μs
tstsI2C Start or repeated Start condition setup time4.7μs
tsthI2C Start or repeated Start condition hold time4μs
tspsI2C Stop condition setup time4μs
tvd(data)Valid data time, SCL low to SDA output valid3.45μs
tvd(ack)Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low3.45μs
CbI2C bus capacitive load400pF
Fast Mode
fsclI2C clock frequency0400kHz
tschI2C clock high time0.6μs
tsclI2C clock low time1.3μs
tspI2C spike time50ns
tsdsI2C serial-data setup time100ns
tsdhI2C serial-data hold time0ns
ticrI2C input rise time20(1)300ns
ticfI2C input fall time20x(Vdd/5.5V)(1)300ns
tocfI2C output fall time, 10-pF to 400-pF bus20x(Vdd/5.5V)(1)300ns
tbufI2C bus free time between Stop and Start1.3μs
tstsI2C Start or repeated Start condition setup time0.6μs
tsthI2C Start or repeated Start condition hold time0.6μs
tspsI2C Stop condition setup time0.6μs
tvd(data)Valid data time, SCL low to SDA output valid0.9μs
tvd(ack)Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low0.9μs
CbI2C bus capacitive load400pF
(1) Cb = Total capacitive load of one bus in pF