Table 1. System Clock Frequencies for Common Audio Sampling Frequencies

Table 2. System Clock Timing

Table 3. Audio Input Data to Analog Output Mapping

Table 4. Audio Interface Timing

Table 5. Oversampling Rate Control

Table 6. Zero-Flag Output Combinations

Table 7. Interface Mode Control

Table 8. Interface Mode Control Pin Assignments

8.3.8.1 Parallel Hardware Control

Four functions are controlled by five pins, MSEL, FMT0, FMT1, DEMP, and MUTE in parallel hardware control mode.

8.3.8.2 SPI Control Interface

The SPI control interface of the PCM1681 and PCM1681-Q1 is a 3-wire synchronous serial port that operates asynchronously to the serial audio interface. The SPI control interface is used to program the on-chip mode registers. The control interface includes MD (pin 4), MC (pin 3), and MS (pin 2). MD is the serial data input, used to program the mode registers. MC is the control port for the serial bit clock, used to shift in the serial data, and MS is the control port for mode control select, which is used to enable the mode control. The SPI control interface is available when MSEL (pin 14) is tied with V_DD and after power-on reset completion.

8.3.8.3 Analog Outputs

The PCM1681 and PCM1681-Q1 include eight independent output channels, V_OUT1 through V_OUT8. These are unbalanced outputs, each capable of driving 3.75 V_PP typical into a 5-kΩ ac load with V_CC = 5 V. The internal output amplifiers for V_OUT1 through V_OUT8 are biased to the dc common voltage, equal to 0.486 V_CC.

The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise-shaping characteristics of the PCM1681 and PCM1681-Q1 ΔΣ DACs. The frequency response of this filter is shown in Figure 12. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for most applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Application and Implementation section of this data sheet.

8.3.8.3.1 V_COM Output

One unbuffered common voltage output pin, V_COM (pin 25), is brought out for decoupling purposes. This pin is nominally biased to the dc common voltage, equal to V_CC/2. If this pin is to be used to bias external circuitry, a voltage follower is required for buffering purposes. Figure 26 shows an example of a 5-V single-supply filter circuit using the V_COM pin for external biasing applications.

NOINDENT:

Example:
R₁: 6.2 kΩ
R₂: 6.8 kΩ
R₃: 430 Ω
C₁: 470 pF
C₂: 4700 pF
A_V: –1.10 (1.45 Vrms Output)
f_C: 70 kHz

Figure 26. Single-Supply Filter Circuit Using V_COM for External Biasing Applications

8.3.8.4 Register Write Operation

All write operations for the serial control port use 16-bit data words. Figure 27 shows the control data word format. The most significant bit is a fixed 0 for the write operation. Seven bits, labeled IDX[6:0], set the register index (or address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0].

Figure 28 shows the functional timing diagram for writing to the serial control port. MS is held at a logic-1 state until a register needs to be written. To start the register write cycle, MS is set to logic-0. 16 clock cycles are then provided on MC, corresponding to the 16 bits of the control data word on MD. After completion of the 16th clock cycle, MS is set to logic-1 to latch the data into the indexed mode control register.

Figure 27. Control Data Word Format for MD

Figure 28. Write Operation Timing

8.3.8.5 Interface Timing Requirements

Figure 29 shows a detailed timing diagram for the serial control interface. Special attention to the setup and hold times is required. Also, t_(MSS) and t_(MSH), which define the minimum delays between the edges of the MS and MC clocks, require special attention. These timing parameters are critical for proper control port operation.

Figure 29. Interface Timing Diagram

8.5.1.1 Slave Address

The PCM1681 and PCM1681-Q1 have seven bits for the respective slave address. The first six bits (MSBs) of the slave address are factory preset to 1001 10. The next bit of the address byte is the device select bit, which can be user-defined using the ADR terminal. A maximum of two PCM1681s or PCM1681-Q1s can be connected on the same bus at one time. Each PCM1681 or PCM1681-Q1 responds when it receives its own slave address.

8.5.1.2 Packet Protocol

A master device must control packet protocol, which consists of a start condition, slave address, read/write bit, data if writing or acknowledge if reading, and stop condition. The PCM1681 and PCM1681-Q1 support only slave receivers and slave transmitters. The details about DATA for write and read operation are described in the following sections.

Figure 30. Basic I²C Framework

8.5.1.3 Write Operation

A master can write to any PCM1681 and PCM1681-Q1 registers using a single access. The master sends a PCM1681 or PCM1681-Q1 slave address with a write bit, a register address, and the data. When undefined registers are accessed, the PCM1681 or PCM1681-Q1 sends an acknowledgment, but the write operation does not occur. Figure 31 is a diagram of the write operation.

Figure 31. Write Operation

8.5.1.4 Read Operation

A master can read any PCM1681 or PCM1681-Q1 register using a single access. The master sends a PCM1681 or PCM1681-Q1 slave address with a read bit after transferring the register address. Then the PCM1681 or PCM1681-Q1 transfers the data in the register specified. Figure 32 is a diagram of the read operation.

NOTE:

The slave address after the repeated start condition must be the same as the previous slave address.

Figure 32. Read Operation

8.5.2.1 User-Programmable Mode Controls

The PCM1681 and PCM1681-Q1 include a number of user-programmable functions which are accessed via control registers. The registers are programmed using the serial control interface which is discussed in the Mode Control section of this data sheet. Table 10 lists the available mode control functions, along with the respective reset default conditions and associated register index.

8.6.2.1 ATx[7:0]: Digital Attenuation Level Setting

where x = 1–8, corresponding to the DAC output V_OUTx. Default value: 1111 1111b

Each DAC output, V_OUT1 through V_OUT8, has a digital attenuation function. The attenuation level can be set from 0 dB to R dB, in S-dB steps. Changes in attenuation levels are made by incrementing or decrementing by one step (S-dB) for every 8/f_S time interval until the programmed attenuation setting is reached. Alternatively, the attenuation level can be set to infinite attenuation (or mute). Range (R) and step (S) are –63 and 0.5, respectively, for DAMS = 0 and –100 and 1, respectively, for DAMS = 1. The DAMS bit is defined in register 13. The attenuation data for each channel can be set individually. The attenuation level can be calculated using the following formula:

where ATx[7:0]_DEC = 0 through 255. For ATx[7:0]_DEC = 0 through 128 with DAMS = 0 or for ATx[7:0]_DEC = 0 through 154 with DAMS = 1, the attenuation is set to infinite attenuation (mute).

8.6.2.2 MUTx: Soft Mute Control

where x = 1–8, corresponding to the DAC output V_OUTx. Default value: 0

The mute bits, MUT1 through MUT8, are used to enable or disable the soft mute function for the corresponding DAC outputs, V_OUT1 through V_OUT8. MUT7 and MUT8 of register 7 and register 18 work as an OR function, either one or both can be used according to the requirements of the application. The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to the infinite-attenuation setting one attenuator step (S-dB) at a time. This provides a quiet, pop-free muting of the DAC output. On returning from soft mute, by setting MUTx = 0, the attenuator is increased one step at a time to the previously programmed attenuator level. The step size, S, is 0.5 dB for DAMS = 0 and 1 dB for DAMS = 1.

8.6.2.3 DACx: DAC Operation Control

where x = 1–8, corresponding to the DAC output V_OUTx. Default value: 0

The DAC operation controls are used to enable and disable the DAC outputs, V_OUT1 through V_OUT8. When DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier input is switched to the dc common voltage (V_COM), equal to V_CC/2. DAC7 and DAC8 of register 8 and register 19 work as an OR function, either one or both can be used according to the requirements of the application.

8.6.2.4 FLT: Digital Filter Roll-Off Control

Default value: 0

The FLT bit allows users to select the digital filter roll-off that is best suited to their application. Two filter roll-off selections are available: sharp or slow. The filter responses for these selections are shown in the Typical Characteristics section of this data sheet.

8.6.2.5 FMT[3:0]: Audio Interface Data Format

Default value: 0101b

The FMT[3:0] bits are used to select the data format for the serial audio interface.

The format details and restrictions related with the system clock are described in the section Audio Data Formats and Timing.

8.6.2.6 SRST: Reset

Default value: 0

The SRST bit is used to enable or disable the soft reset function. The operation is the same as the power-on-reset function with the exception of the reset period, which is 1024 system clocks for the SRST function. All registers are initialized.

8.6.2.7 ZREV: Zero-Flag Polarity Select

Default value: 0

The ZREV bit allows the user to select the polarity of the zero-flag pins.

8.6.2.8 DREV: Output Phase Select

Default value: 0

The DREV bit allows the user to select the phase of the analog output signal.

8.6.2.9 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function

Default value: 00b

The DMF[1:0] bits select the sampling frequency used for the digital de-emphasis function when it is enabled. The de-emphasis curves are shown in the Typical Characteristics section of this data sheet. The preceding table shows the available sampling frequencies.

8.6.2.10 DMC: Digital De-Emphasis All-Channel Function Control

Default value: 0

The DMC bit is used to enable or disable the de-emphasis function for all channels.

8.6.2.11 REV[8:1]: Output Phase Select per Channel

Where x = 1 – 8, corresponding to the DAC output V_OUTx. Default value: 1

The REVx bit allows the user to select the phase of the analog output signal per channel when DREV = 1 is set on Register 10.

8.6.2.12 OVER: Oversampling Rate Control

Default value: 0

8.6.2.13 FLTx: Digital Filter Roll-Off Control per DATA Group

Where x = 1 – 4, corresponding to the DATAx. Default value: 1

The FLTx bit allows the user to select the digital filter roll-off characteristic per 2 channels when FLT = 1 is set, so that it is best suited to the application. Two filter roll-off sections are available: sharp or slow. The filter responses for these selections are shown in the Typical Characteristics section.

8.6.2.14 DAMS: Digital Attenuation Mode Select

Default value: 0

The DAMS bit is used to select the digital attenuation mode.

8.6.2.15 AZRO[1:0]: Zero-Flag Channel-Combination Select

Default value: 00b

The AZRO[1:0] bits are used to select the zero-flag channel combinations for ZR1 and ZR2.

8.6.2.16 ZERO[8:1]: Zero-Detect Status (Read-Only, I²C Interface Only)

Default value: N/A

The ZERO[8:1] bits show the status of zero detect for each channel. The status is set to 1 by detecting a zero state without regard to the ZREV bit setting.