7.3.1 Analog Outputs

The PCM1789 includes a two-channel DAC, with a pair of differential voltage outputs pins. The full-scale output voltage is (1.6 × VCC1) V_PP in differential output mode. A dc-coupled load is allowed in addition to an ac-coupled load, if the load resistance conforms to the specification. These balanced outputs are each capable of driving 0.8 VCC1 (4 V_PP) typical into a 5-kΩ ac-coupled or 15-kΩ dc-coupled load with VCC1 = +5 V. The internal output amplifiers for VOUTL and VOUTR are biased to the dc common voltage, equal to 0.5 VCC1.

The output amplifiers include an RC continuous-time filter that helps to reduce the out-of-band noise energy present at the DAC outputs as a result of the noise shaping characteristics of the PCM1789 delta-sigma (ΔΣ) DACs. The frequency response of this filter is shown in the Analog Filter Characteristic (Figure 11) of the Typical Characteristics. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for most applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Application Information section.

7.3.2 Voltage Reference VCOM

The PCM1789 includes a pin for the common-mode voltage output, VCOM. This pin should be connected to the analog ground via a decoupling capacitor. This pin can also be used to bias external high-impedance circuits, if they are required.

7.3.3 System Clock Input

The PCM1789 requires an external system clock input applied at the SCKI input for DAC operation. The system clock operates at an integer multiple of the sampling frequency, or f_S. The multiples supported in DAC operation include 128 f_S, 192 f_S, 256 f_S, 384 f_S, 512 f_S, 768 f_S, and 1152 f_S. Details for these system clock multiples are shown in Table 1. The System Clock Timing Requirements table shows the SCKI timing requirements.

Figure 19. System Clock Timing Diagram

7.3.4 Reset Operation

The PCM1789 has both an internal power-on reset circuit and an external reset circuit. The sequences for both reset circuits are shown in Figure 20 and Figure 21. Figure 20 illustrates the timing at the internal power-on reset. Initialization is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset is released after 3846 SCKI clock cycles from power-on, if RST is held high and SCKI is provided. VOUTx from the DAC is forced to the VCOM level initially (that is, 0.5 × VCC1) and settles at a specified level according to the rising VCC. If synchronization among SCKI, BCK, and LRCK is maintained, VOUT provides an output that corresponds to DIN after 3846 SCKI clocks from power-on. If the synchronization is not held, the internal reset is not released, and both operating modes are maintained at reset and power-down states. After synchronization forms again, the DAC returns to normal operation with the previous sequences.

Figure 21 illustrates a timing diagram at the external reset. RST accepts an externally-forced reset with RST low, and provides a device reset and power-down state that achieves the lowest power dissipation state available in the PCM1789. If RST goes from high to low under synchronization among SCKI, BCK, and LRCK, the internal reset is asserted, all registers and memory are reset, and finally, the PCM1789 enters into all power-down states. At the same time, VOUT is immediately forced into the AGND1 level. To begin normal operation again, toggle RST high; the same power-up sequence is performed as the power-on reset shown in Figure 20.

The PCM1789 does not require particular power-on sequences for VCC and VDD; it allows VDD on and then VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings, however, simultaneous power-on is recommended for avoiding unexpected responses on VOUTx. Figure 20 illustrates the response for VCC on with VDD on.

Figure 20. Power-On-Reset Timing Requirements

Figure 21. External Reset Timing Requirements

7.3.5 ZERO Flag

The PCM1789 has two ZERO flag pins (ZERO1 and ZERO2) that can be assigned to the combinations shown in Table 2. Zero flag combinations are selected through the AZRO bit in control register 22 (16h). If the input data of all the assigned channels remain at '0' for 1024 sampling periods (LRCK clock periods), the ZERO1/2 bits are set to a high level, logic '1' state. Furthermore, if the input data of any of the assigned channels read '1', the ZERO1/2 are set to a low level, logic '0' state, immediately. Zero data detection is supported for 16-/20-/24-bit data width, but is not supported for 32-bit data width.

The active polarity of the zero flag output can be inverted through the ZREV bit in control register 22 (16h). The reset default is active high for zero detection.

In parallel hardware control mode, ZERO1 and ZERO2 are fixed with combination A, shown in Table 2.

Note that the ZERO2 pin is multiplexed with AMUTEO pin. Selection of ZERO2 or AMUTEO can be changed through the MZSEL bit in control register 22 (16h). The default setting after reset is the selection of ZERO2.

7.3.6 AMUTE Control

The PCM1789 has an AMUTE control input, status output pins, and functionality. AMUTEI is the input control pin of the internal analog mute circuit. An AMUTEI low input causes the DAC output to cut-off from the digital input and forces it to the center level (0.5 VCC1). AMUTEO is the status output pin of the internal analog mute circuit. AMUTEO low indicates the analog mute control circuit is active because of a programmed condition (such as an SCKI halt, asynchronous detect, zero detect, or by the DAC disable command) that forces the DAC outputs to a center level. Because AMUTEI is not terminated internally and AMUTEO is an open-drain output, pull-ups by the appropriate resistors are required for proper operation.

Note that the AMUTEO pin is multiplexed with the ZERO2 pin. The desired pin is selected through the MZSEL bit in control register 22 (16h). The default setting is the selection of the ZERO2 pin.

Additionally, because the AMUTEI pin control and power-down control in register (OPEDA when high, PSMDA when low) do not function together, AMUTEI takes priority over power-down control. Therefore, power-down control is ignored during AMUTEI low, and AMUTEI low forces the DAC output to a center level (0.5 VCC1) even if power-down control is asserted.

7.3.7 Three-Wire (SPI) Serial Control

The PCM1789 includes an SPI-compatible serial port that operates asynchronously with the audio serial interface. The control interface consists of MD/SDA/DEMP, MC/SCL/FMT, and MS/ADR0/RSV. MD is the serial data input used to program the mode control registers. MC is the serial bit clock that shifts the data into the control port. MS is the select input used to enable the mode control port.

7.3.8 Control Data Word Format

All single write operations via the serial control port use 16-bit data words. Figure 22 shows the control data word format. The first bit (fixed at '0') is for write operation. After the first bit are seven other bits, labeled ADR[6:0], that set the register address for the write operation. ADR6 is determined by the status of the MODE pin. ADR5 is determined by the state of the ADR5/ADR1/RSV pin. A maximum of four PCM1789s can be connected on the same bus at any one time. Each PCM1789 responds when receiving its own register address. The eight least significant bits (LSBs), D[7:0] on MD, contain the data to be written to the register address specified by ADR[6:0].

Figure 22. Control Data Word Format for MD

7.3.9 Register Write Operation

Figure 23 shows the functional timing diagram for single write operations on the serial control port. MS is held at a high state until a register is to be written to. To start the register write cycle, MS is set to a low state. 16 clocks are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the 16th clock cycle has been completed, MS is set high to latch the data into the indexed mode control register.

In addition to single write operations, the PCM1789 also supports multiple write operations, which can be performed by sending the N-bytes (where N ≤ 9) of the 8-bit register data that follow after the first 16-bit register address and register data, while keeping the MC clocks and MS at a low state. Ending a multiple write operation can be accomplished by setting MS to a high state.

1. X = don't care.

Figure 23. Register Write Operation

7.3.10 Timing Requirements

Figure 24 shows a detailed timing diagram for the three-wire serial control interface. These timing parameters are critical for proper control port operation.

Figure 24. Three-Wire Serial Control Interface Timing

7.3.11 Two-wire (I²C) Serial Control

The PCM1789 supports an I²C-compatible serial bus and data transmission protocol for fast mode configured as a slave device. This protocol is explained in the I²C specification 2.0.

The PCM1789 has a 7-bit slave address, as shown in Figure 25. The first five bits are the most significant bits (MSBs) of the slave address and are factory-preset to 10011. The next two bits of the address byte are selectable bits that can be set by MS/ADR0/RSV and ADR5/ADR1/RSV. A maximum of four PCM1789s can be connected on the same bus at any one time. Each PCM1789 responds when it receives its own slave address.

Figure 25. Slave Address

7.3.12 Packet Protocol

A master device must control the packet protocol, which consists of a start condition, a slave address with the read/write bit, data if a write operation is required, an acknowledgment if a read operation is required, and a stop condition. The PCM1789 supports both slave receiver and transmitter functions. Details about DATA for both write and read operations are described in Figure 26.

1. R/W: Read operation if 1; write operation otherwise.

2. ACK: Acknowledgment of a byte if 0, not Acknowledgment of a byte if 1.

3. DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.

Figure 26. I²C Packet Control Protocol

7.3.13 Write Operation

The PCM1789 supports a receiver function. A master device can write to any PCM1789 register using single or multiple accesses. The master sends a PCM1789 slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When valid data are received, the index register automatically increments by one. When the register address reaches &h4F, the next value is &h40. When undefined registers are accessed, the PCM1789 does not send an acknowledgment. Figure 27 illustrates a diagram of the write operation. The register address and write data are in 8-bit, MSB-first format.

NOTE: M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.

Figure 27. Framework for Write Operation

7.3.14 Read Operation

A master device can read the registers of the PCM1789. The value of the register address is stored in an indirect index register in advance. The master sends the PCM1789 slave address with a read bit after storing the register address. Then the PCM1789 transfers the data that the index register points to. Figure 28 shows a diagram of the read operation.

1. The slave address after the repeated start condition must be the same as the previous slave address.

NOTE: M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge, NACK = Not acknowledge, and Sp = Stop condition.

Figure 28. Framework for Read Operation

7.4.1 Sampling Mode

The PCM1789 supports three sampling modes (single rate, dual rate, and quad rate) in DAC operation. In single rate mode, the DAC operates at an oversampling frequency of x128 (except when SCKI = 128 f_S and 192 f_S); this mode is supported for sampling frequencies less than 50 kHz. In dual rate mode, the DAC operates at an oversampling frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad rate mode, the DAC operates at an oversampling frequency of x32. The sampling mode is automatically selected according to the ratio of system clock frequency and sampling frequency by default (that is, single rate for 512 f_S, 768 f_S, and 1152 f_S; dual rate for 256 f_S and 384 f_S; and quad rate for 128 f_S and 192 f_S), but manual selection is also possible for specified combinations through the serial mode control register.

Table 3 and Figure 29 show the relationship among the oversampling rate (OSR) of the digital filter and ΔΣ modulator, the noise-free shaped bandwidth, and each sampling mode setting.

Figure 29. ΔΣ Modulator and Digital Filter Characteristic

7.4.2 Audio Serial Port Operation

The PCM1789 audio serial port consists of three signals: BCK, LRCK, and DIN. BCK is a bit clock input. LRCK is a left/right word clock or frame synchronization clock input. DIN is the audio data input for VOUTL/R.

7.4.3 Audio Data Interface Formats and Timing

The PCM1789 supports six audio data interface formats: 16-/20-/24-/32-bit I²S, 16-/20-/24-/32-bit left-justified, 24-bit right-justified, 16-bit right-justified, 24-bit left-justified mode DSP, and 24-bit I²S mode DSP. In the case of I²S, left-justified, and right-justified data formats, 64 BCKs, 48 BCKs, and 32 BCKs per LRCK period are supported; however, 48 BCKs are limited to 192/384/768 f_S SCKI, and 32 BCKs are limited to 16-bit right-justified only. The audio data formats are selected by MC/SCL/FMT in hardware control mode and by the FMTDA[2:0] bits in control register 17 (11h) in software control mode. All data must be in binary twos complement and MSB first.

Table 4 summarizes the applicable formats and describes the relationships among them and the respective restrictions with mode control. Figure 30 through Figure 34 show six audio interface data formats.

Figure 30. Audio Data Format: 16-/20-/24-/32-Bit I²S
(N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29)

Figure 31. Audio Data Format: 16-/20-/24-/32-Bit Left-Justified
(N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29)

Figure 32. Audio Data Format: 24-Bit Right-Justified

Figure 33. Audio Data Format: 16-Bit Right-Justified

Figure 34. Audio Data Format: 24-Bit DSP Format

7.4.4 Audio Interface Timing

Figure 35 and Audio Interface Timing Requirements describe the detailed audio interface timing specifications.

Figure 35. Audio Interface Timing Diagram for Left-Justified, Right-Justified, I²S, and DSP Data Formats

7.4.5 Synchronization with the Digital Audio System

The PCM1789 operates under the system clock (SCKI) and the audio sampling rate (LRCK). Therefore, SCKI and LRCK must have a specific relationship. The PCM1789 does not need a specific phase relationship between the audio interface clocks (LRCK, BCK) and the system clock (SCKI), but does require a specific frequency relationship (ratiometric) between LRCK, BCK, and SCKI.

If the relationship between SCKI and LRCK changes more than ±2 BCK clocks because of jitter, sampling frequency change, etc., the DAC internal operation stops within 1/f_S, and the analog output is forced into VCOM (0.5 VCC1) until re-synchronization among SCKI, LRCK, and BCK completes, and then either 38/f_S (single, dual rate) or 29/f_S (quad rate) passes. In the event the change is less than ±2 BCKs, re-synchronization does not occur, and this analog output control and discontinuity does not occur.

Figure 36 shows the DAC analog output during loss of synchronization. During undefined data periods, some noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined (or zero) data to normal data creates a discontinuity of data on the analog outputs, which may then generate some noise in the audio signal.

The DAC outputs (VOUTx) hold the previous state if the system clock halts, but the asynchronous and re-synchronization processes will occur after the system clock resumes.

Figure 36. DAC Outputs During Loss of Synchronization

7.4.6 MODE Control

The PCM1789 includes three mode control interfaces with three oversampling configurations, depending on the input state of the MODE pin, as shown in Table 5. The pull-up and pull-down resistors must be 220 kΩ ±5%.

The input state of the MODE pin is sampled at the moment of power-on, or during a low-to-high transition of the RST pin, with the system clock input. Therefore, input changes after reset are ignored until the next power-on or reset. From the mode control selection described in Table 5, the functions of four pins are changed, as shown in Table 6.

In serial mode control, the actual mode control is performed by register writes (and reads) through the SPI- or I²C-compatible serial control port. In parallel mode control, two specific functions are controlled directly through the high/low control of two specific pins, as described in the following section.

7.4.7 Parallel Hardware Control

The functions shown in Table 7 and Table 8 are controlled by two pins, DEMP and FMT, in parallel hardware control mode. The DEMP pin controls the 44.1-kHz digital de-emphasis function of both channels. The FMT pin controls the audio interface format for both channels.

7.5.1 Control Register Definitions (Software Mode Only)

The PCM1789 has many user-programmable functions that are accessed via control registers, and are programmed through the SPI or I²C serial control port. Table 9 shows the available mode control functions along with reset default conditions and associated register addresses. Table 10 lists the register map.

7.5.2 Register Definitions